Lines Matching refs:priv
130 static void bcmstb_spi_hw_set_parms(struct bcmstb_spi_priv *priv) in bcmstb_spi_hw_set_parms() argument
132 writel(SPBR_MIN, &priv->regs->spcr0_lsb); in bcmstb_spi_hw_set_parms()
133 writel(BITS_PER_WORD << 2 | SPI_MODE_3, &priv->regs->spcr0_msb); in bcmstb_spi_hw_set_parms()
163 struct bcmstb_spi_priv *priv = dev_get_priv(bus); in bcmstb_spi_probe() local
165 priv->regs = plat->base[HIF_MSPI]; in bcmstb_spi_probe()
166 priv->bspi = plat->base[BSPI]; in bcmstb_spi_probe()
167 priv->hif_spi_intr2 = plat->base[HIF_SPI_INTR2]; in bcmstb_spi_probe()
168 priv->cs_reg = plat->base[CS_REG]; in bcmstb_spi_probe()
169 priv->default_cs = 0; in bcmstb_spi_probe()
170 priv->curr_cs = -1; in bcmstb_spi_probe()
171 priv->tx_slot = 0; in bcmstb_spi_probe()
172 priv->rx_slot = 0; in bcmstb_spi_probe()
173 memset(priv->saved_cmd, 0, NUM_CDRAM); in bcmstb_spi_probe()
174 priv->saved_cmd_len = 0; in bcmstb_spi_probe()
175 priv->saved_din_addr = NULL; in bcmstb_spi_probe()
177 debug("spi_xfer: tx regs: 0x%p\n", &priv->regs->txram[0]); in bcmstb_spi_probe()
178 debug("spi_xfer: rx regs: 0x%p\n", &priv->regs->rxram[0]); in bcmstb_spi_probe()
181 writel(1, priv->bspi + BSPI_MAST_N_BOOT_CTRL); in bcmstb_spi_probe()
182 readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL); in bcmstb_spi_probe()
185 bcmstb_spi_disable_interrupt(priv->hif_spi_intr2, 0xffffffff); in bcmstb_spi_probe()
186 bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, 0xffffffff); in bcmstb_spi_probe()
187 bcmstb_spi_enable_interrupt(priv->hif_spi_intr2, in bcmstb_spi_probe()
191 writel(0, &priv->regs->spcr1_lsb); in bcmstb_spi_probe()
192 writel(0, &priv->regs->spcr1_msb); in bcmstb_spi_probe()
193 writel(0, &priv->regs->newqp); in bcmstb_spi_probe()
194 writel(0, &priv->regs->endqp); in bcmstb_spi_probe()
195 writel(HIF_MSPI_SPCR2_SPIFIE_MASK, &priv->regs->spcr2); in bcmstb_spi_probe()
196 writel(0, &priv->regs->spcr3); in bcmstb_spi_probe()
198 bcmstb_spi_hw_set_parms(priv); in bcmstb_spi_probe()
203 static void bcmstb_spi_submit(struct bcmstb_spi_priv *priv, bool done) in bcmstb_spi_submit() argument
206 writel(0, &priv->regs->newqp); in bcmstb_spi_submit()
208 debug("WR ENDQP: %d\n", priv->tx_slot - 1); in bcmstb_spi_submit()
209 writel(priv->tx_slot - 1, &priv->regs->endqp); in bcmstb_spi_submit()
212 debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1, in bcmstb_spi_submit()
213 readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80); in bcmstb_spi_submit()
214 writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80, in bcmstb_spi_submit()
215 &priv->regs->cdram[priv->tx_slot - 1]); in bcmstb_spi_submit()
219 if (priv->curr_cs != priv->default_cs) { in bcmstb_spi_submit()
221 priv->default_cs); in bcmstb_spi_submit()
222 writel((readl(priv->cs_reg) & ~0xff) | (1 << priv->default_cs), in bcmstb_spi_submit()
223 priv->cs_reg); in bcmstb_spi_submit()
224 readl(priv->cs_reg); in bcmstb_spi_submit()
226 priv->curr_cs = priv->default_cs; in bcmstb_spi_submit()
230 writel((readl(&priv->regs->write_lock) & in bcmstb_spi_submit()
232 &priv->regs->write_lock); in bcmstb_spi_submit()
233 readl(&priv->regs->write_lock); in bcmstb_spi_submit()
242 &priv->regs->spcr2); in bcmstb_spi_submit()
245 static int bcmstb_spi_wait(struct bcmstb_spi_priv *priv) in bcmstb_spi_wait() argument
248 u32 status = readl(&priv->regs->mspi_status); in bcmstb_spi_wait()
253 status = readl(&priv->regs->mspi_status); in bcmstb_spi_wait()
256 writel(readl(&priv->regs->mspi_status) & ~1, &priv->regs->mspi_status); in bcmstb_spi_wait()
257 bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, in bcmstb_spi_wait()
272 struct bcmstb_spi_priv *priv = dev_get_priv(bus); in bcmstb_spi_xfer() local
273 struct bcmstb_hif_mspi_regs *regs = priv->regs; in bcmstb_spi_xfer()
277 debug("spi_xfer: chip select: %x\n", readl(priv->cs_reg) & 0xff); in bcmstb_spi_xfer()
284 priv->saved_din_addr); in bcmstb_spi_xfer()
285 priv->saved_din_addr = NULL; in bcmstb_spi_xfer()
286 priv->saved_cmd_len = 0; in bcmstb_spi_xfer()
287 memset(priv->saved_cmd, 0, NUM_CDRAM); in bcmstb_spi_xfer()
304 priv->tx_slot = 0; in bcmstb_spi_xfer()
305 priv->rx_slot = 0; in bcmstb_spi_xfer()
321 priv->saved_cmd_len = len; in bcmstb_spi_xfer()
322 memcpy(priv->saved_cmd, out_bytes, priv->saved_cmd_len); in bcmstb_spi_xfer()
327 if (priv->saved_din_addr == din) { in bcmstb_spi_xfer()
335 ret = bcmstb_spi_xfer(dev, priv->saved_cmd_len * 8, in bcmstb_spi_xfer()
336 priv->saved_cmd, NULL, in bcmstb_spi_xfer()
344 priv->saved_din_addr = din; in bcmstb_spi_xfer()
349 priv->rx_slot = priv->tx_slot; in bcmstb_spi_xfer()
351 while (priv->tx_slot < NUM_CDRAM && tx_len > 0) { in bcmstb_spi_xfer()
352 bcmstb_spi_hw_set_parms(priv); in bcmstb_spi_xfer()
353 debug("WR TXRAM[%d]: %02x\n", priv->tx_slot, in bcmstb_spi_xfer()
356 ®s->txram[priv->tx_slot << 1]); in bcmstb_spi_xfer()
357 debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e); in bcmstb_spi_xfer()
358 writel(0x8e, ®s->cdram[priv->tx_slot]); in bcmstb_spi_xfer()
359 priv->tx_slot++; in bcmstb_spi_xfer()
375 bcmstb_spi_submit(priv, tx_len == 0); in bcmstb_spi_xfer()
377 if (bcmstb_spi_wait(priv) == -ETIMEDOUT) { in bcmstb_spi_xfer()
382 priv->tx_slot %= NUM_CDRAM; in bcmstb_spi_xfer()
385 while (priv->rx_slot < NUM_CDRAM && rx_len > 0) { in bcmstb_spi_xfer()
387 readl(®s->rxram[(priv->rx_slot << 1) in bcmstb_spi_xfer()
391 priv->rx_slot, in_bytes[len - rx_len]); in bcmstb_spi_xfer()
392 priv->rx_slot++; in bcmstb_spi_xfer()
400 writel((readl(&priv->regs->write_lock) & in bcmstb_spi_xfer()
402 &priv->regs->write_lock); in bcmstb_spi_xfer()
403 readl(&priv->regs->write_lock); in bcmstb_spi_xfer()