Lines Matching refs:priv
180 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv) in _stm32_qspi_disable() argument
182 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); in _stm32_qspi_disable()
185 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv) in _stm32_qspi_enable() argument
187 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); in _stm32_qspi_enable()
190 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv) in _stm32_qspi_wait_for_not_busy() argument
192 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY) in _stm32_qspi_wait_for_not_busy()
196 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv) in _stm32_qspi_wait_for_complete() argument
198 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF)) in _stm32_qspi_wait_for_complete()
202 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv) in _stm32_qspi_wait_for_ftf() argument
204 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF)) in _stm32_qspi_wait_for_ftf()
208 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size) in _stm32_qspi_set_flash_size() argument
211 clrsetbits_le32(&priv->regs->dcr, in _stm32_qspi_set_flash_size()
216 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) in _stm32_qspi_gen_ccr() argument
220 u32 mode = priv->mode; in _stm32_qspi_gen_ccr()
221 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK); in _stm32_qspi_gen_ccr()
242 if (priv->command & CMD_HAS_DATA) in _stm32_qspi_gen_ccr()
245 if (priv->command & CMD_HAS_DUMMY) in _stm32_qspi_gen_ccr()
246 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK) in _stm32_qspi_gen_ccr()
249 if (priv->command & CMD_HAS_ADR) { in _stm32_qspi_gen_ccr()
259 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv, in _stm32_qspi_enable_mmap() argument
264 priv->command = flash->read_opcode | CMD_HAS_ADR | CMD_HAS_DATA in _stm32_qspi_enable_mmap()
266 priv->dummycycles = flash->read_dummy; in _stm32_qspi_enable_mmap()
268 unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv); in _stm32_qspi_enable_mmap()
271 _stm32_qspi_wait_for_not_busy(priv); in _stm32_qspi_enable_mmap()
273 writel(ccr_reg, &priv->regs->ccr); in _stm32_qspi_enable_mmap()
275 priv->dummycycles = 0; in _stm32_qspi_enable_mmap()
278 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv) in _stm32_qspi_disable_mmap() argument
280 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT); in _stm32_qspi_disable_mmap()
283 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv, in _stm32_qspi_set_xfer_length() argument
286 writel(length - 1, &priv->regs->dlr); in _stm32_qspi_set_xfer_length()
289 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg) in _stm32_qspi_start_xfer() argument
291 writel(cr_reg, &priv->regs->ccr); in _stm32_qspi_start_xfer()
293 if (priv->command & CMD_HAS_ADR) in _stm32_qspi_start_xfer()
294 writel(priv->address, &priv->regs->ar); in _stm32_qspi_start_xfer()
297 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, in _stm32_qspi_xfer() argument
304 _stm32_qspi_enable_mmap(priv, flash); in _stm32_qspi_xfer()
307 _stm32_qspi_disable_mmap(priv); in _stm32_qspi_xfer()
332 priv->command = dout[0] | CMD_HAS_DATA; in _stm32_qspi_xfer()
335 priv->address = (dout[1] << 16) | in _stm32_qspi_xfer()
337 priv->command |= CMD_HAS_ADR; in _stm32_qspi_xfer()
342 priv->dummycycles = (words - 4) * 8; in _stm32_qspi_xfer()
343 priv->command |= CMD_HAS_DUMMY; in _stm32_qspi_xfer()
348 priv->command &= ~(CMD_HAS_DATA); in _stm32_qspi_xfer()
353 u32 ccr_reg = _stm32_qspi_gen_ccr(priv); in _stm32_qspi_xfer()
357 _stm32_qspi_wait_for_not_busy(priv); in _stm32_qspi_xfer()
359 if (priv->command & CMD_HAS_DATA) in _stm32_qspi_xfer()
360 _stm32_qspi_set_xfer_length(priv, words); in _stm32_qspi_xfer()
362 _stm32_qspi_start_xfer(priv, ccr_reg); in _stm32_qspi_xfer()
365 __func__, priv->regs->ccr, priv->regs->ar); in _stm32_qspi_xfer()
367 if (priv->command & CMD_HAS_DATA) { in _stm32_qspi_xfer()
368 _stm32_qspi_wait_for_ftf(priv); in _stm32_qspi_xfer()
374 writeb(dout[i], &priv->regs->dr); in _stm32_qspi_xfer()
380 _stm32_qspi_wait_for_complete(priv); in _stm32_qspi_xfer()
382 _stm32_qspi_wait_for_not_busy(priv); in _stm32_qspi_xfer()
386 u32 ccr_reg = _stm32_qspi_gen_ccr(priv); in _stm32_qspi_xfer()
390 _stm32_qspi_wait_for_not_busy(priv); in _stm32_qspi_xfer()
392 _stm32_qspi_set_xfer_length(priv, words); in _stm32_qspi_xfer()
394 _stm32_qspi_start_xfer(priv, ccr_reg); in _stm32_qspi_xfer()
397 priv->regs->ccr, priv->regs->ar, priv->regs->dlr); in _stm32_qspi_xfer()
403 din[i] = readb(&priv->regs->dr); in _stm32_qspi_xfer()
453 struct stm32_qspi_priv *priv = dev_get_priv(bus); in stm32_qspi_probe() local
460 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base; in stm32_qspi_probe()
462 priv->max_hz = plat->max_hz; in stm32_qspi_probe()
478 priv->clock_rate = clk_get_rate(&clk); in stm32_qspi_probe()
479 if (priv->clock_rate < 0) { in stm32_qspi_probe()
481 return priv->clock_rate; in stm32_qspi_probe()
486 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); in stm32_qspi_probe()
498 struct stm32_qspi_priv *priv; in stm32_qspi_claim_bus() local
503 priv = dev_get_priv(bus); in stm32_qspi_claim_bus()
506 _stm32_qspi_set_flash_size(priv, flash->size); in stm32_qspi_claim_bus()
508 _stm32_qspi_enable(priv); in stm32_qspi_claim_bus()
515 struct stm32_qspi_priv *priv; in stm32_qspi_release_bus() local
519 priv = dev_get_priv(bus); in stm32_qspi_release_bus()
521 _stm32_qspi_disable(priv); in stm32_qspi_release_bus()
529 struct stm32_qspi_priv *priv; in stm32_qspi_xfer() local
534 priv = dev_get_priv(bus); in stm32_qspi_xfer()
537 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout, in stm32_qspi_xfer()
544 struct stm32_qspi_priv *priv = dev_get_priv(bus); in stm32_qspi_set_speed() local
549 u32 qspi_clk = priv->clock_rate; in stm32_qspi_set_speed()
562 _stm32_qspi_wait_for_not_busy(priv); in stm32_qspi_set_speed()
564 clrsetbits_le32(&priv->regs->cr, in stm32_qspi_set_speed()
570 clrsetbits_le32(&priv->regs->dcr, in stm32_qspi_set_speed()
574 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, in stm32_qspi_set_speed()
582 struct stm32_qspi_priv *priv = dev_get_priv(bus); in stm32_qspi_set_mode() local
584 _stm32_qspi_wait_for_not_busy(priv); in stm32_qspi_set_mode()
587 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
589 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
597 priv->mode |= SPI_RX_QUAD; in stm32_qspi_set_mode()
599 priv->mode |= SPI_RX_DUAL; in stm32_qspi_set_mode()
601 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL); in stm32_qspi_set_mode()
604 priv->mode |= SPI_TX_QUAD; in stm32_qspi_set_mode()
606 priv->mode |= SPI_TX_DUAL; in stm32_qspi_set_mode()
608 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL); in stm32_qspi_set_mode()
610 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode); in stm32_qspi_set_mode()