Lines Matching refs:priv
76 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
103 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) in rockchip_combphy_is_ready() argument
105 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
111 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
117 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) in rockchip_combphy_pcie_init() argument
122 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
123 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
125 dev_err(priv->dev, "failed to init phy for pcie\n"); in rockchip_combphy_pcie_init()
130 if (priv->cfg->force_det_out) { in rockchip_combphy_pcie_init()
131 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
133 writel(val, priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
139 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) in rockchip_combphy_usb3_init() argument
141 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_usb3_init()
144 if (dev_read_bool(priv->dev, "rockchip,dis-u3otg0-port")) { in rockchip_combphy_usb3_init()
145 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); in rockchip_combphy_usb3_init()
147 } else if (dev_read_bool(priv->dev, "rockchip,dis-u3otg1-port")) { in rockchip_combphy_usb3_init()
148 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); in rockchip_combphy_usb3_init()
150 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rockchip_combphy_usb3_init()
155 param_write(priv->pipe_grf, &cfg->u3otg0_clamp_dis, true); in rockchip_combphy_usb3_init()
158 if (priv->cfg->combphy_cfg) { in rockchip_combphy_usb3_init()
159 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_usb3_init()
161 dev_err(priv->dev, "failed to init phy for usb3\n"); in rockchip_combphy_usb3_init()
169 static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) in rockchip_combphy_sata_init() argument
173 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sata_init()
174 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sata_init()
176 dev_err(priv->dev, "failed to init phy for sata\n"); in rockchip_combphy_sata_init()
184 static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) in rockchip_combphy_sgmii_init() argument
188 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sgmii_init()
189 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sgmii_init()
191 dev_err(priv->dev, "failed to init phy for sgmii\n"); in rockchip_combphy_sgmii_init()
205 struct rockchip_combphy_priv *priv; in rockchip_combphy_usb3_uboot_init() local
228 priv = dev_get_priv(udev); in rockchip_combphy_usb3_uboot_init()
229 priv->mode = PHY_TYPE_USB3; in rockchip_combphy_usb3_uboot_init()
230 cfg = priv->cfg->grfcfg; in rockchip_combphy_usb3_uboot_init()
232 rockchip_combphy_usb3_init(priv); in rockchip_combphy_usb3_uboot_init()
233 reset_deassert(&priv->phy_rst); in rockchip_combphy_usb3_uboot_init()
236 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_usb3_uboot_init()
238 if (priv->mode == PHY_TYPE_USB3) { in rockchip_combphy_usb3_uboot_init()
240 priv, val, in rockchip_combphy_usb3_uboot_init()
244 dev_err(priv->dev, "wait phy status ready timeout\n"); in rockchip_combphy_usb3_uboot_init()
245 param_write(priv->phy_grf, &cfg->usb_mode_set, false); in rockchip_combphy_usb3_uboot_init()
247 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); in rockchip_combphy_usb3_uboot_init()
254 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); in rockchip_combphy_usb3_uboot_init()
259 static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) in rockchip_combphy_set_mode() argument
261 switch (priv->mode) { in rockchip_combphy_set_mode()
263 rockchip_combphy_pcie_init(priv); in rockchip_combphy_set_mode()
266 rockchip_combphy_usb3_init(priv); in rockchip_combphy_set_mode()
269 rockchip_combphy_sata_init(priv); in rockchip_combphy_set_mode()
273 return rockchip_combphy_sgmii_init(priv); in rockchip_combphy_set_mode()
275 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_set_mode()
284 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); in rockchip_combphy_init() local
285 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
288 ret = clk_enable(&priv->ref_clk); in rockchip_combphy_init()
292 ret = rockchip_combphy_set_mode(priv); in rockchip_combphy_init()
296 reset_deassert(&priv->phy_rst); in rockchip_combphy_init()
299 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_init()
304 clk_disable(&priv->ref_clk); in rockchip_combphy_init()
311 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); in rockchip_combphy_exit() local
312 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_exit()
315 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); in rockchip_combphy_exit()
317 reset_assert(&priv->phy_rst); in rockchip_combphy_exit()
318 clk_disable(&priv->ref_clk); in rockchip_combphy_exit()
325 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); in rockchip_combphy_xlate() local
332 priv->mode = args->args[0]; in rockchip_combphy_xlate()
344 struct rockchip_combphy_priv *priv) in rockchip_combphy_parse_dt() argument
355 priv->pipe_grf = syscon_get_regmap(syscon); in rockchip_combphy_parse_dt()
362 priv->phy_grf = syscon_get_regmap(syscon); in rockchip_combphy_parse_dt()
364 ret = clk_get_by_index(dev, 0, &priv->ref_clk); in rockchip_combphy_parse_dt()
367 return PTR_ERR(&priv->ref_clk); in rockchip_combphy_parse_dt()
370 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); in rockchip_combphy_parse_dt()
378 regmap_write(priv->pipe_grf, vals[0], in rockchip_combphy_parse_dt()
386 struct rockchip_combphy_priv *priv = dev_get_priv(udev); in rockchip_combphy_probe() local
389 priv->mmio = (void __iomem *)dev_read_addr(udev); in rockchip_combphy_probe()
390 if (IS_ERR(priv->mmio)) in rockchip_combphy_probe()
391 return PTR_ERR(priv->mmio); in rockchip_combphy_probe()
399 priv->dev = udev; in rockchip_combphy_probe()
400 priv->mode = PHY_TYPE_SATA; in rockchip_combphy_probe()
401 priv->cfg = phy_cfg; in rockchip_combphy_probe()
403 return rockchip_combphy_parse_dt(udev, priv); in rockchip_combphy_probe()
407 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) in rk3528_combphy_cfg() argument
409 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg()
412 switch (priv->mode) { in rk3528_combphy_cfg()
415 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
418 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
420 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
421 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
422 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
423 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
427 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
430 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
433 val = readl(priv->mmio + 0x200); in rk3528_combphy_cfg()
436 writel(val, priv->mmio + 0x200); in rk3528_combphy_cfg()
439 val = readl(priv->mmio + 0x20c); in rk3528_combphy_cfg()
442 writel(val, priv->mmio + 0x20c); in rk3528_combphy_cfg()
444 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
445 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
446 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
449 dev_err(priv->dev, "incompatible PHY type\n"); in rk3528_combphy_cfg()
453 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
454 if (priv->mode == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
456 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
459 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
462 val = readl(priv->mmio + 0x108); in rk3528_combphy_cfg()
465 writel(val, priv->mmio + 0x108); in rk3528_combphy_cfg()
501 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) in rk3562_combphy_cfg() argument
503 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg()
506 switch (priv->mode) { in rk3562_combphy_cfg()
509 val = readl(priv->mmio + (0x1f << 2)); in rk3562_combphy_cfg()
512 writel(val, priv->mmio + 0x7c); in rk3562_combphy_cfg()
514 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
515 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
516 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
517 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
521 val = readl(priv->mmio + (0x1f << 2)); in rk3562_combphy_cfg()
524 writel(val, priv->mmio + 0x7c); in rk3562_combphy_cfg()
527 val = readl(priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
530 writel(val, priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
533 val = readl(priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
536 writel(val, priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
539 writel(0x4, priv->mmio + (0xb << 2)); in rk3562_combphy_cfg()
542 val = readl(priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
545 writel(val, priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
548 writel(0x32, priv->mmio + (0x11 << 2)); in rk3562_combphy_cfg()
551 writel(0xf0, priv->mmio + (0xa << 2)); in rk3562_combphy_cfg()
554 writel(0x0e, priv->mmio + (0x14 << 2)); in rk3562_combphy_cfg()
556 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
557 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
558 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
559 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
562 pr_err("%s, phy-type %d\n", __func__, priv->mode); in rk3562_combphy_cfg()
566 clk_set_rate(&priv->ref_clk, 100000000); in rk3562_combphy_cfg()
567 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
569 if (priv->mode == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
571 val = readl(priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
574 writel(val, priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
577 writel(0x4, priv->mmio + (0xb << 2)); in rk3562_combphy_cfg()
579 val = readl(priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
582 writel(val, priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
584 writel(0x32, priv->mmio + (0x11 << 2)); in rk3562_combphy_cfg()
585 writel(0xf0, priv->mmio + (0xa << 2)); in rk3562_combphy_cfg()
588 if (dev_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3562_combphy_cfg()
589 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3562_combphy_cfg()
590 if (priv->mode == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
591 val = readl(priv->mmio + (0xc << 2)); in rk3562_combphy_cfg()
593 writel(val, priv->mmio + (0xc << 2)); in rk3562_combphy_cfg()
595 val = readl(priv->mmio + (0xd << 2)); in rk3562_combphy_cfg()
597 writel(val, priv->mmio + (0xd << 2)); in rk3562_combphy_cfg()
601 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3562_combphy_cfg()
602 val = readl(priv->mmio + (0x7 << 2)); in rk3562_combphy_cfg()
604 writel(val, priv->mmio + (0x7 << 2)); in rk3562_combphy_cfg()
644 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) in rk3568_combphy_cfg() argument
646 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
649 switch (priv->mode) { in rk3568_combphy_cfg()
652 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
655 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
657 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
658 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
659 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
660 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
664 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
667 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
670 val = readl(priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
673 writel(val, priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
676 val = readl(priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
679 writel(val, priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
682 writel(0x4, priv->mmio + (0xb << 2)); in rk3568_combphy_cfg()
685 val = readl(priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
688 writel(val, priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
691 writel(0x32, priv->mmio + (0x11 << 2)); in rk3568_combphy_cfg()
694 writel(0xf0, priv->mmio + (0xa << 2)); in rk3568_combphy_cfg()
697 writel(0x0e, priv->mmio + (0x14 << 2)); in rk3568_combphy_cfg()
699 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
702 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
705 writel(0x41, priv->mmio + 0x38); in rk3568_combphy_cfg()
706 writel(0x8F, priv->mmio + 0x18); in rk3568_combphy_cfg()
707 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
708 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
709 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
710 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
711 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
714 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
715 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
716 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
717 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
720 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
721 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
722 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
723 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
724 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
727 pr_err("%s, phy-type %d\n", __func__, priv->mode); in rk3568_combphy_cfg()
732 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
734 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3568_combphy_cfg()
735 val = readl(priv->mmio + (0x7 << 2)); in rk3568_combphy_cfg()
737 writel(val, priv->mmio + (0x7 << 2)); in rk3568_combphy_cfg()
787 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) in rk3588_combphy_cfg() argument
789 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
792 switch (priv->mode) { in rk3588_combphy_cfg()
794 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
795 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
796 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
797 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
801 val = readl(priv->mmio + (0x1f << 2)); in rk3588_combphy_cfg()
804 writel(val, priv->mmio + 0x7c); in rk3588_combphy_cfg()
807 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
810 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
813 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
816 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
819 writel(0x4, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
822 val = readl(priv->mmio + (0x5 << 2)); in rk3588_combphy_cfg()
825 writel(val, priv->mmio + (0x5 << 2)); in rk3588_combphy_cfg()
828 writel(0x32, priv->mmio + (0x11 << 2)); in rk3588_combphy_cfg()
831 writel(0xf0, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
834 writel(0x0d, priv->mmio + (0x14 << 2)); in rk3588_combphy_cfg()
836 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
837 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
838 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
842 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
845 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
847 writel(0x8F, priv->mmio + (0x06 << 2)); in rk3588_combphy_cfg()
849 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
850 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
851 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
852 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
853 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
854 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
859 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
864 clk_set_rate(&priv->ref_clk, 100000000); in rk3588_combphy_cfg()
865 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
866 if (priv->mode == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
868 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
871 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
875 writel(val, priv->mmio + (0x1b << 2)); in rk3588_combphy_cfg()
879 writel(val, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
881 writel(val, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
883 writel(val, priv->mmio + (0xd << 2)); in rk3588_combphy_cfg()
925 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) in rk3576_combphy_cfg() argument
927 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3576_combphy_cfg()
930 switch (priv->mode) { in rk3576_combphy_cfg()
932 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3576_combphy_cfg()
933 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3576_combphy_cfg()
934 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3576_combphy_cfg()
935 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3576_combphy_cfg()
939 val = readl(priv->mmio + (0x1f << 2)); in rk3576_combphy_cfg()
942 writel(val, priv->mmio + 0x7c); in rk3576_combphy_cfg()
945 val = readl(priv->mmio + (0x0e << 2)); in rk3576_combphy_cfg()
948 writel(val, priv->mmio + (0x0e << 2)); in rk3576_combphy_cfg()
951 val = readl(priv->mmio + (0x20 << 2)); in rk3576_combphy_cfg()
954 writel(val, priv->mmio + (0x20 << 2)); in rk3576_combphy_cfg()
957 writel(0x4, priv->mmio + (0xb << 2)); in rk3576_combphy_cfg()
960 val = readl(priv->mmio + (0x5 << 2)); in rk3576_combphy_cfg()
963 writel(val, priv->mmio + (0x5 << 2)); in rk3576_combphy_cfg()
966 writel(0x32, priv->mmio + (0x11 << 2)); in rk3576_combphy_cfg()
969 writel(0xf0, priv->mmio + (0xa << 2)); in rk3576_combphy_cfg()
972 writel(0x0d, priv->mmio + (0x14 << 2)); in rk3576_combphy_cfg()
974 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3576_combphy_cfg()
975 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3576_combphy_cfg()
976 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3576_combphy_cfg()
980 val = readl(priv->mmio + (0x0e << 2)); in rk3576_combphy_cfg()
983 writel(val, priv->mmio + (0x0e << 2)); in rk3576_combphy_cfg()
985 writel(0x8F, priv->mmio + (0x06 << 2)); in rk3576_combphy_cfg()
987 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3576_combphy_cfg()
988 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3576_combphy_cfg()
989 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3576_combphy_cfg()
990 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3576_combphy_cfg()
991 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3576_combphy_cfg()
992 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3576_combphy_cfg()
997 dev_err(priv->dev, "incompatible PHY type\n"); in rk3576_combphy_cfg()
1002 clk_set_rate(&priv->ref_clk, 100000000); in rk3576_combphy_cfg()
1003 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3576_combphy_cfg()
1004 if (priv->mode == PHY_TYPE_PCIE) { in rk3576_combphy_cfg()
1006 writel(0xc0, priv->mmio + 0x74); in rk3576_combphy_cfg()
1009 val = readl(priv->mmio + (0x20 << 2)); in rk3576_combphy_cfg()
1012 writel(val, priv->mmio + (0x20 << 2)); in rk3576_combphy_cfg()
1015 writel(0x4c, priv->mmio + (0x1b << 2)); in rk3576_combphy_cfg()
1018 writel(0x90, priv->mmio + (0xa << 2)); in rk3576_combphy_cfg()
1019 writel(0x43, priv->mmio + (0xb << 2)); in rk3576_combphy_cfg()
1020 writel(0x88, priv->mmio + (0xc << 2)); in rk3576_combphy_cfg()
1021 writel(0x56, priv->mmio + (0xd << 2)); in rk3576_combphy_cfg()
1066 static int rv1126b_combphy_cfg(struct rockchip_combphy_priv *priv) in rv1126b_combphy_cfg() argument
1068 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rv1126b_combphy_cfg()
1071 switch (priv->mode) { in rv1126b_combphy_cfg()
1074 val = readl(priv->mmio + (0x1f << 2)); in rv1126b_combphy_cfg()
1077 writel(val, priv->mmio + 0x7c); in rv1126b_combphy_cfg()
1080 val = readl(priv->mmio + (0x0e << 2)); in rv1126b_combphy_cfg()
1083 writel(val, priv->mmio + (0x0e << 2)); in rv1126b_combphy_cfg()
1086 val = readl(priv->mmio + (0x20 << 2)); in rv1126b_combphy_cfg()
1089 writel(val, priv->mmio + (0x20 << 2)); in rv1126b_combphy_cfg()
1092 writel(0x4, priv->mmio + (0x0b << 2)); in rv1126b_combphy_cfg()
1095 val = readl(priv->mmio + (0x5 << 2)); in rv1126b_combphy_cfg()
1098 writel(val, priv->mmio + (0x5 << 2)); in rv1126b_combphy_cfg()
1101 writel(0x32, priv->mmio + (0x11 << 2)); in rv1126b_combphy_cfg()
1104 writel(0xf0, priv->mmio + (0x0a << 2)); in rv1126b_combphy_cfg()
1107 writel(0x0e, priv->mmio + (0x14 << 2)); in rv1126b_combphy_cfg()
1109 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rv1126b_combphy_cfg()
1110 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rv1126b_combphy_cfg()
1111 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rv1126b_combphy_cfg()
1112 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rv1126b_combphy_cfg()
1115 dev_err(priv->dev, "incompatible PHY type\n"); in rv1126b_combphy_cfg()
1119 clk_set_rate(&priv->ref_clk, 100000000); in rv1126b_combphy_cfg()
1120 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rv1126b_combphy_cfg()