143 	struct fsl_qspi_priv priv;  member
170 static void qspi_set_lut(struct fsl_qspi_priv *priv)  in qspi_set_lut()  argument
172 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_set_lut()
176 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);  in qspi_set_lut()
177 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);  in qspi_set_lut()
181 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |  in qspi_set_lut()
183 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
184 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
185 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
190 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
196 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
201 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
207 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
211 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
212 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
216 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |  in qspi_set_lut()
219 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
220 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
221 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
226 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |  in qspi_set_lut()
231 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
236 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
241 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
242 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
243 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
247 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
250 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
251 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
252 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
257 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |  in qspi_set_lut()
262 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
267 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
278 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |  in qspi_set_lut()
281 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
285 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
286 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
290 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |  in qspi_set_lut()
293 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
294 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
295 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
299 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |  in qspi_set_lut()
310 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |  in qspi_set_lut()
315 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |  in qspi_set_lut()
320 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |  in qspi_set_lut()
325 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |  in qspi_set_lut()
335 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
339 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
349 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
353 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
357 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);  in qspi_set_lut()
358 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);  in qspi_set_lut()
368 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)  in qspi_ahb_invalid()  argument
370 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_ahb_invalid()
373 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_invalid()
375 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_ahb_invalid()
384 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_ahb_invalid()
388 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)  in qspi_ahb_read()  argument
390 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_ahb_read()
394 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_read()
396 	qspi_write32(priv->flags, &regs->mcr,  in qspi_ahb_read()
400 	rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);  in qspi_ahb_read()
404 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_ahb_read()
407 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)  in qspi_enable_ddr_mode()  argument
410 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_enable_ddr_mode()
412 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_enable_ddr_mode()
414 	qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);  in qspi_enable_ddr_mode()
417 	reg2 = qspi_read32(priv->flags, &regs->smpr);  in qspi_enable_ddr_mode()
420 	qspi_write32(priv->flags, &regs->smpr, reg2);  in qspi_enable_ddr_mode()
427 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_enable_ddr_mode()
443 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)  in qspi_init_ahb_read()  argument
445 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_init_ahb_read()
448 	qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
449 	qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
450 	qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
451 	qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |  in qspi_init_ahb_read()
455 	qspi_write32(priv->flags, &regs->buf0ind, 0);  in qspi_init_ahb_read()
456 	qspi_write32(priv->flags, &regs->buf1ind, 0);  in qspi_init_ahb_read()
457 	qspi_write32(priv->flags, &regs->buf2ind, 0);  in qspi_init_ahb_read()
463 	qspi_write32(priv->flags, &regs->bfgencr,  in qspi_init_ahb_read()
467 	qspi_enable_ddr_mode(priv);  in qspi_init_ahb_read()
473 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)  in qspi_op_rdbank()  argument
475 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdbank()
478 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdbank()
479 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdbank()
482 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdbank()
484 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdbank()
486 	if (priv->cur_seqid == QSPI_CMD_BRRD)  in qspi_op_rdbank()
491 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdbank()
495 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdbank()
501 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdbank()
503 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdbank()
506 			qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdbank()
507 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdbank()
513 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdbank()
517 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)  in qspi_op_rdid()  argument
519 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdid()
523 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdid()
524 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdid()
527 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdid()
529 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdid()
531 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdid()
533 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdid()
540 		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdid()
542 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_rdid()
552 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdid()
556 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)  in qspi_op_read()  argument
558 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_read()
564 	if (priv->cur_seqid == QSPI_CMD_RDAR)  in qspi_op_read()
569 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_read()
570 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_read()
573 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_read()
575 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_read()
580 		qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_read()
585 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_read()
588 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_read()
596 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_read()
606 		qspi_write32(priv->flags, &regs->mcr,  in qspi_op_read()
607 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_read()
611 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_read()
614 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)  in qspi_op_write()  argument
616 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_write()
621 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_write()
622 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_write()
625 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_write()
631 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
633 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
636 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
638 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
641 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_write()
643 			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_write()
646 		qspi_write32(priv->flags, &regs->mcr,  in qspi_op_write()
647 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_write()
653 	if (priv->cur_seqid == QSPI_CMD_WRAR)  in qspi_op_write()
656 	if (priv->cur_seqid == QSPI_CMD_BRWR)  in qspi_op_write()
658 	else if (priv->cur_seqid == QSPI_CMD_WREAR)  in qspi_op_write()
662 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_write()
664 	qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_write()
679 		qspi_write32(priv->flags, &regs->tbdr, data);  in qspi_op_write()
683 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
685 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
688 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_write()
691 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)  in qspi_op_rdsr()  argument
693 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdsr()
696 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdsr()
697 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdsr()
700 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdsr()
702 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdsr()
704 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdsr()
706 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdsr()
712 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdsr()
714 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdsr()
717 			qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdsr()
718 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdsr()
724 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdsr()
727 static void qspi_op_erase(struct fsl_qspi_priv *priv)  in qspi_op_erase()  argument
729 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_erase()
733 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_erase()
734 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_erase()
737 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_erase()
739 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_erase()
740 	qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_erase()
742 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
744 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
747 	if (priv->cur_seqid == QSPI_CMD_SE) {  in qspi_op_erase()
748 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
750 	} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {  in qspi_op_erase()
751 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
754 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
757 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_erase()
760 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,  in qspi_xfer()  argument
771 			priv->cur_seqid = *(u8 *)dout;  in qspi_xfer()
776 			priv->sf_addr = wr_sfaddr;  in qspi_xfer()
777 			qspi_op_write(priv, (u8 *)dout, bytes);  in qspi_xfer()
781 		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||  in qspi_xfer()
782 		    priv->cur_seqid == QSPI_CMD_RDAR) {  in qspi_xfer()
783 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;  in qspi_xfer()
784 		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||  in qspi_xfer()
785 			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {  in qspi_xfer()
786 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;  in qspi_xfer()
787 			qspi_op_erase(priv);  in qspi_xfer()
788 		} else if (priv->cur_seqid == QSPI_CMD_PP ||  in qspi_xfer()
789 			   priv->cur_seqid == QSPI_CMD_WRAR) {  in qspi_xfer()
791 		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||  in qspi_xfer()
792 			 (priv->cur_seqid == QSPI_CMD_WREAR)) {  in qspi_xfer()
800 		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {  in qspi_xfer()
802 			qspi_ahb_read(priv, din, bytes);  in qspi_xfer()
804 			qspi_op_read(priv, din, bytes);  in qspi_xfer()
806 		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {  in qspi_xfer()
807 			qspi_op_read(priv, din, bytes);  in qspi_xfer()
808 		} else if (priv->cur_seqid == QSPI_CMD_RDID)  in qspi_xfer()
809 			qspi_op_rdid(priv, din, bytes);  in qspi_xfer()
810 		else if (priv->cur_seqid == QSPI_CMD_RDSR)  in qspi_xfer()
811 			qspi_op_rdsr(priv, din, bytes);  in qspi_xfer()
813 		else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||  in qspi_xfer()
814 			 (priv->cur_seqid == QSPI_CMD_RDEAR)) {  in qspi_xfer()
815 			priv->sf_addr = 0;  in qspi_xfer()
816 			qspi_op_rdbank(priv, din, bytes);  in qspi_xfer()
822 	if ((priv->cur_seqid == QSPI_CMD_SE) ||  in qspi_xfer()
823 	    (priv->cur_seqid == QSPI_CMD_PP) ||  in qspi_xfer()
824 	    (priv->cur_seqid == QSPI_CMD_BE_4K) ||  in qspi_xfer()
825 	    (priv->cur_seqid == QSPI_CMD_WREAR) ||  in qspi_xfer()
826 	    (priv->cur_seqid == QSPI_CMD_BRWR))  in qspi_xfer()
827 		qspi_ahb_invalid(priv);  in qspi_xfer()
833 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)  in qspi_module_disable()  argument
837 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in qspi_module_disable()
842 	qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);  in qspi_module_disable()
845 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)  in qspi_cfg_smpr()  argument
849 	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);  in qspi_cfg_smpr()
852 	qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);  in qspi_cfg_smpr()
893 	qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;  in spi_setup_slave()
897 	qspi->priv.regs = regs;  in spi_setup_slave()
905 	qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;  in spi_setup_slave()
909 	mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);  in spi_setup_slave()
915 	qspi_write32(qspi->priv.flags, &regs->mcr,  in spi_setup_slave()
919 	qspi_cfg_smpr(&qspi->priv,  in spi_setup_slave()
934 	qspi_write32(qspi->priv.flags, &regs->sfa1ad,  in spi_setup_slave()
936 	qspi_write32(qspi->priv.flags, &regs->sfa2ad,  in spi_setup_slave()
938 	qspi_write32(qspi->priv.flags, &regs->sfb1ad,  in spi_setup_slave()
940 	qspi_write32(qspi->priv.flags, &regs->sfb2ad,  in spi_setup_slave()
943 	qspi_set_lut(&qspi->priv);  in spi_setup_slave()
946 	qspi_init_ahb_read(&qspi->priv);  in spi_setup_slave()
949 	qspi_module_disable(&qspi->priv, 0);  in spi_setup_slave()
976 	return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);  in spi_xfer()
998 	struct fsl_qspi_priv *priv = dev_get_priv(bus);  in fsl_qspi_probe()  local
1006 	priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;  in fsl_qspi_probe()
1007 	priv->flags = plat->flags;  in fsl_qspi_probe()
1009 	priv->speed_hz = plat->speed_hz;  in fsl_qspi_probe()
1015 	priv->amba_base[0] = (u32)plat->amba_base;  in fsl_qspi_probe()
1016 	priv->amba_total_size = (u32)plat->amba_total_size;  in fsl_qspi_probe()
1017 	priv->flash_num = plat->flash_num;  in fsl_qspi_probe()
1018 	priv->num_chipselect = plat->num_chipselect;  in fsl_qspi_probe()
1021 	ret = wait_for_bit_le32(&priv->regs->sr,  in fsl_qspi_probe()
1032 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in fsl_qspi_probe()
1038 	qspi_write32(priv->flags, &priv->regs->mcr,  in fsl_qspi_probe()
1042 	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |  in fsl_qspi_probe()
1055 	amba_size_per_chip = priv->amba_total_size >>  in fsl_qspi_probe()
1056 			     (priv->num_chipselect >> 1);  in fsl_qspi_probe()
1057 	for (i = 1 ; i < priv->num_chipselect ; i++)  in fsl_qspi_probe()
1058 		priv->amba_base[i] =  in fsl_qspi_probe()
1059 			amba_size_per_chip + priv->amba_base[i - 1];  in fsl_qspi_probe()
1071 	qspi_write32(priv->flags, &priv->regs->sfa1ad,  in fsl_qspi_probe()
1072 		     priv->amba_base[0] + amba_size_per_chip);  in fsl_qspi_probe()
1073 	switch (priv->num_chipselect) {  in fsl_qspi_probe()
1077 		qspi_write32(priv->flags, &priv->regs->sfa2ad,  in fsl_qspi_probe()
1078 			     priv->amba_base[1]);  in fsl_qspi_probe()
1079 		qspi_write32(priv->flags, &priv->regs->sfb1ad,  in fsl_qspi_probe()
1080 			     priv->amba_base[1] + amba_size_per_chip);  in fsl_qspi_probe()
1081 		qspi_write32(priv->flags, &priv->regs->sfb2ad,  in fsl_qspi_probe()
1082 			     priv->amba_base[1] + amba_size_per_chip);  in fsl_qspi_probe()
1085 		qspi_write32(priv->flags, &priv->regs->sfa2ad,  in fsl_qspi_probe()
1086 			     priv->amba_base[2]);  in fsl_qspi_probe()
1087 		qspi_write32(priv->flags, &priv->regs->sfb1ad,  in fsl_qspi_probe()
1088 			     priv->amba_base[3]);  in fsl_qspi_probe()
1089 		qspi_write32(priv->flags, &priv->regs->sfb2ad,  in fsl_qspi_probe()
1090 			     priv->amba_base[3] + amba_size_per_chip);  in fsl_qspi_probe()
1094 		      priv->num_chipselect);  in fsl_qspi_probe()
1095 		qspi_module_disable(priv, 1);  in fsl_qspi_probe()
1099 	qspi_set_lut(priv);  in fsl_qspi_probe()
1102 	qspi_init_ahb_read(priv);  in fsl_qspi_probe()
1105 	qspi_module_disable(priv, 0);  in fsl_qspi_probe()
1168 	struct fsl_qspi_priv *priv;  in fsl_qspi_xfer()  local
1172 	priv = dev_get_priv(bus);  in fsl_qspi_xfer()
1174 	return qspi_xfer(priv, bitlen, dout, din, flags);  in fsl_qspi_xfer()
1179 	struct fsl_qspi_priv *priv;  in fsl_qspi_claim_bus()  local
1185 	priv = dev_get_priv(bus);  in fsl_qspi_claim_bus()
1188 	ret = wait_for_bit_le32(&priv->regs->sr,  in fsl_qspi_claim_bus()
1199 	priv->cur_amba_base = priv->amba_base[slave_plat->cs];  in fsl_qspi_claim_bus()
1201 	qspi_module_disable(priv, 0);  in fsl_qspi_claim_bus()
1208 	struct fsl_qspi_priv *priv;  in fsl_qspi_release_bus()  local
1212 	priv = dev_get_priv(bus);  in fsl_qspi_release_bus()
1214 	qspi_module_disable(priv, 1);  in fsl_qspi_release_bus()