phy: rockchip: naneng-combphy: Set clamp for rv1126b usb3

The RV1126B USB3.0 PHY clamp default value is 1'b0 which
means that clamp enable. This patch sets clamp value to
1'b1 for USB3.0 function.

phy: rockchip: naneng-combphy: Set clamp for rv1126b usb3

The RV1126B USB3.0 PHY clamp default value is 1'b0 which
means that clamp enable. This patch sets clamp value to
1'b1 for USB3.0 function.

Sync from Rockchip kernel develop-6.1-fpga branch, refer to
commit: "8dd495374585" (phy: rockchip: naneng-combphy: Set clamp for rv1126b usb3)

Change-Id: I4c3d635f2cf194dc6140655c74db1efc809bbfd3
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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phy: rockchip: naneng-combphy: add support for rv1126b usb3

Sync from Rockchip kernel develop-6.1-fpga branch, refer to
commit: "45ff333f6ae4" (phy: rockchip: naneng-combphy: Add support for rv1126b

phy: rockchip: naneng-combphy: add support for rv1126b usb3

Sync from Rockchip kernel develop-6.1-fpga branch, refer to
commit: "45ff333f6ae4" (phy: rockchip: naneng-combphy: Add support for rv1126b usb3)

Change-Id: I937f3212b33e8a74492769443c85bd96bb399dd2
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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phy: rockchip: naneng-combphy: rk3562 support rockchip,ext-refclk

Change-Id: I01bd12c64a2d345b377322eaa4f3a7d7af108ddc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

phy: rockchip: naneng-combphy: Fix force detect out

Change-Id: I8d4b13795d7f15bb0af42544b085fd75cdea67f7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip: naneng-combphy: fix phy device mismatch

The uclass_get_device_by_driver() API always finds the first device in
DT probed, however, it may not the PHY that associate with USB download

phy: rockchip: naneng-combphy: fix phy device mismatch

The uclass_get_device_by_driver() API always finds the first device in
DT probed, however, it may not the PHY that associate with USB download
controller, if mismathed, the below errors would be printed in terminal.

download key pressed... entering download mode...
RKUSB: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x1d5a000
failed to enable ep0out
failed to start <NULL>: -110
g_dnl_register: failed!, error: -110
g_dnl_register failedEnter rockusb failed, fallback to bootrom...

So passed the PHY physical address and loop to match the correct PHY
device to fix it.

Fixes: 14d5da7dccb8 ("phy: rockchip: naneng-combphy: Add usb3 phy init for rockusb")
Change-Id: Ib65a104008d6302dca09cc081a3457b3d55e0323
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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phy: rockchip: naneng-combphy: Support disable usb3 port

The usb3 host controller support one usb3 port and one
usb2 port, and these two ports can work independently.

+------

phy: rockchip: naneng-combphy: Support disable usb3 port

The usb3 host controller support one usb3 port and one
usb2 port, and these two ports can work independently.

+------+ +----------+
+----------------+ | USB2 |---->| USB2 PHY |
| |---->| PORT | +----------+
| USB3 HOST CTRL | +------+
| |---->| USB3 | +----------+
+----------------+ | PROT |---->| COMBO PHY|
+------+ +----------+

This patch support usb3 host to disable usb3 port
and only support usb2 port.

In addition, for RK3576, it use pipe_phymode to select
MMU for PCIe/SATA/USB controllers, and the default
pipe_phymode value is 2'b00 which used for PCIe mode.
So it needs to set pipe_phymode for usb even if only
use usb2 port.

Change-Id: I26b8b5445cf153719944442195421e10e88c269b
Signed-off-by: William Wu <william.wu@rock-chips.com>

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phy: rockchip: naneng-combphy: Support RK3576

Change-Id: Ib7f895311a085f928f927f8f77c3a057b9f175c5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

phy: rockchip: naneng-combphy: Build depends on platform config

When build for RK3588 with CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY enabled:

size drivers/phy/phy-rockchip-naneng-combphy.o

before:
te

phy: rockchip: naneng-combphy: Build depends on platform config

When build for RK3588 with CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY enabled:

size drivers/phy/phy-rockchip-naneng-combphy.o

before:
text data bss dec hex filename
6539 120 0 6659 1a03 drivers/phy/phy-rockchip-naneng-combphy.o

after:
text data bss dec hex filename
3217 120 0 3337 d09 drivers/phy/phy-rockchip-naneng-combphy.o

Change-Id: I6d4bf8168bd2b89750def8491ebfeb135373f763
Signed-off-by: William Wu <william.wu@rock-chips.com>

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phy: rockchip: naneng-combphy: Fix U3 Rx squelch for RK3528/RK3562/RK3568

This patch adjust the RK3528/RK3562/RK3568 U3 Rx squelch
input filler bandwidth to 3'b110 which is used for rx_lfps,
reduce

phy: rockchip: naneng-combphy: Fix U3 Rx squelch for RK3528/RK3562/RK3568

This patch adjust the RK3528/RK3562/RK3568 U3 Rx squelch
input filler bandwidth to 3'b110 which is used for rx_lfps,
reduce the bandwidth to avoid filtering valid superspeed
data.

With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on these platforms.

Change-Id: I81666e098f9ee6f3a7789cb6f89bf3de687e0930
Signed-off-by: William Wu <william.wu@rock-chips.com>

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phy: rockchip: naneng-combphy: Add usb3 phy init for rockusb

This patch init usb3 phy for rockusb gadget to support super
speed download image. Note that if usb3 phy has been initializd
successfully

phy: rockchip: naneng-combphy: Add usb3 phy init for rockusb

This patch init usb3 phy for rockusb gadget to support super
speed download image. Note that if usb3 phy has been initializd
successfully, we should select clk_usb3otg0_pipe as the source
clock for usb3 otg controller. And if it fail to init usb3 phy,
we should select clk_usb3otg0_utmi as the source clock for usb3
otg controller.

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Signed-off-by: william.wu <william.wu@rock-chips.com>
Change-Id: I39d5c863f4f54b27343d033aaea73fb39f873c0d

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phy: rockchip-naneng-combo: Support phy grf reset

1.Assert phy-reset via PIPEPHY GRF instead of asserting via CRU that
would be useless when PD_PHP is off.
2.RK3562 change to use phy grf reset

Port

phy: rockchip-naneng-combo: Support phy grf reset

1.Assert phy-reset via PIPEPHY GRF instead of asserting via CRU that
would be useless when PD_PHP is off.
2.RK3562 change to use phy grf reset

Porting from commit f67f48f03950 ("phy: rockchip-naneng-combo: Support
phy grf reset") in Rockchip Kernel-5.10.

Change-Id: I599f7ec38193db408691c474b0da54ba8a69eb8f
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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phy: rockchip: naneng-combphy: Modify rk3562 phy 100M refclk configuration

Change-Id: Ifebd50d24b1ea057ac03249e0bd7eb1028e8bef0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

phy: rockchip-naneng-combphy: support for rk3562

This adds support for RK3562 PCIE and USB3.

Change-Id: Ifce7d4554a76c6d4cc3dc11a8baabee07fe1f3bc
Signed-off-by: Frank Wang <frank.wang@rock-chips.co

phy: rockchip-naneng-combphy: support for rk3562

This adds support for RK3562 PCIE and USB3.

Change-Id: Ifce7d4554a76c6d4cc3dc11a8baabee07fe1f3bc
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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phy: rockchip: naneng-combphy: Support for rk3528

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I710556d3ba57818e965213a3295cce3ea37c3a5f

phy: rockchip: naneng-combophy: adjust Rx squelch for RK3588 U3

This patch adjust the RK3588 U3 Rx squelch input filler
bandwidth which is used for rx_lfps, reduce the bandwidth
to avoid filtering v

phy: rockchip: naneng-combophy: adjust Rx squelch for RK3588 U3

This patch adjust the RK3588 U3 Rx squelch input filler
bandwidth which is used for rx_lfps, reduce the bandwidth
to avoid filtering valid superspeed data.

With this patch, it can fix the issue that Kingston U3 Disk
read error on RK3588 platforms with the following log:

[ 71.507131][ T404] usb 6-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 71.524942][ T404] usb 6-1: New USB device found, idVendor=0951, idProduct=1666, bcdDevice= 1.10
[ 71.524971][ T404] usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 71.524984][ T404] usb 6-1: Product: DataTraveler 3.0
[ 71.524995][ T404] usb 6-1: Manufacturer: Kingston
[ 71.525006][ T404] usb 6-1: SerialNumber: 08606E6D3FDDB090680C42D4
[ 71.532019][ T404] usb-storage 6-1:1.0: USB Mass Storage device detected
[ 71.537183][ T404] scsi host0: usb-storage 6-1:1.0
[ 72.541060][ T9] scsi 0:0:0:0: Direct-Access Kingston DataTraveler 3.0 PMAP PQ: 0 ANSI: 6
[ 72.542143][ T9] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 72.542545][ T222] sd 0:0:0:0: [sda] 30277632 512-byte logical blocks: (15.5 GB/14.4 GiB)
[ 72.542800][ T222] sd 0:0:0:0: [sda] Write Protect is off
[ 72.543171][ T222] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 72.620179][ T222] sda: sda4
[ 72.623249][ T222] sd 0:0:0:0: [sda] Attached SCSI removable disk
[ 72.797197][ T2097] usb 6-1: reset SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 72.814719][ C3] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK cmd_age=0s
[ 72.814735][ C3] sd 0:0:0:0: [sda] tag#0 CDB: Read(10) 28 00 00 00 11 20 00 01 00 00
[ 72.814743][ C3] blk_update_request: I/O error, dev sda, sector 4384 op 0x0:(READ) flags 0x80700 phys_seg 29 prio class 0

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I97ab26dcc4a48e7314586d5169b9fada10cf0787

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phy: rockchip: naneng-combphy: Add config for rk3588 sata

This patch aims to configure sata for better compatibility.
1. Enable the adaptive Continuous Time Linear Equalizer (CTLE).
2. Set tx_rterm

phy: rockchip: naneng-combphy: Add config for rk3588 sata

This patch aims to configure sata for better compatibility.
1. Enable the adaptive Continuous Time Linear Equalizer (CTLE).
2. Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Id4ca907ef653512705d90c9d3a077fd8a061a0f3

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phy: naneng-combophy: Remove redundant set_mode

Change-Id: Ia688979181a370455112f6db8dacf598fcdcbfe2
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

phy: naneng-combophy: Update combophy paramter for pcie pll

The config can get better signal for pcie2 combophy clk output.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I0646646

phy: naneng-combophy: Update combophy paramter for pcie pll

The config can get better signal for pcie2 combophy clk output.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I06466461fd81d6ca4e867914d65002594eeee16f

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phy: rockchip: naneng-combphy: Add config for rk3588 usb3

This patch aims to configure usb for better compatibility.
1. Set ssc downward spread spectrum.
2. Enable the adaptive Continuous Time Linea

phy: rockchip: naneng-combphy: Add config for rk3588 usb3

This patch aims to configure usb for better compatibility.
1. Set ssc downward spread spectrum.
2. Enable the adaptive Continuous Time Linear Equalizer (CTLE).
3. Adjusts the PLL the parameters for USB Rx to pass the
Receiver Jitter Tolerance Test, and it's helpful to
improve the USB 3.0 signal compatibility.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I9c8c7db29178074b0b906012accc26ccf7202a34

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phy: rockchip: naneng-combphy: Add config option for pcie1ln-sel

Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is
in PHP_GRF_PCIESEL_CON.
pcie1l0_sel
Select the signal form PH

phy: rockchip: naneng-combphy: Add config option for pcie1ln-sel

Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is
in PHP_GRF_PCIESEL_CON.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY

Change-Id: I2410e7e0298ec7f01cc12b00a1d543fbe0cb50d0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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phy: rockchip: naneng-combphy: Using 100M refclk for rk3588 combo-phy

100MHz refclock signal is good, so it is fixed as this frequency point.

Change-Id: I99117de28980066833e43ee417f3390d30c6f291
Si

phy: rockchip: naneng-combphy: Using 100M refclk for rk3588 combo-phy

100MHz refclock signal is good, so it is fixed as this frequency point.

Change-Id: I99117de28980066833e43ee417f3390d30c6f291
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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phy: rockchip: naneng-combphy: Support rk3588

The PHY clock is fixed at 100MHz

Change-Id: I1331cf964ebf427f1d4def209c527158c96bfbe2
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

phy: rockchip: naneng-combphy: Adjust PLL parameters for rk3568 usb3

When do the USB 3.0 Receiver Jitter Tolerance Test on
RK3568 EVB, it fails at Sj Frequency 2.0/4.9/10.0 [MHz].
This patch adjusts

phy: rockchip: naneng-combphy: Adjust PLL parameters for rk3568 usb3

When do the USB 3.0 Receiver Jitter Tolerance Test on
RK3568 EVB, it fails at Sj Frequency 2.0/4.9/10.0 [MHz].
This patch adjusts the PLL parameters for USB to pass
the Receiver Jitter Tolerance Test, and it's helpful to
improve the USB 3.0 signal compatibility.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I8f9e346c5d43e8cc79767b3951b0ed82a39e1578

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phy: rockchip: fix reset and clk error for naneng combphy

The combphy has two resets. If we get reset by index 0, we will
get apb-reset rather than phy-reset. Besides, the delault ref-clk
of combphy

phy: rockchip: fix reset and clk error for naneng combphy

The combphy has two resets. If we get reset by index 0, we will
get apb-reset rather than phy-reset. Besides, the delault ref-clk
of combphy is 25MHz.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I57349b6a28a6e5c15f86f24030bbf85d50be94e8

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drivers: phy: add naneng combphy for rk3568

RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram of
the complex connect

drivers: phy: add naneng combphy for rk3568

RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram of
the complex connection.

+----------------+
| | +------+
| USB3 OTG CTRL0 |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY0 |
+----------------+ | | | |
| | | | +------------+
| SATA CTRL0 |---->| |
| | +------+
+----------------+

+----------------+
| | +------+
| USB3 HOST CTRL1|---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY1 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL1 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | | +------+
| QSGMII CTRL |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY2 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL2 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | |
| PCIe2 1-Lane |---
| |
+----------------+

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I9c035c9df201e3c923c14398e48582e6e877f6fc

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