117 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)  in ti_spi_set_speed()  argument
124 		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;  in ti_spi_set_speed()
133 	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,  in ti_spi_set_speed()
134 	       &priv->base->clk_ctrl);  in ti_spi_set_speed()
136 	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);  in ti_spi_set_speed()
139 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)  in ti_qspi_cs_deactivate()  argument
141 	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);  in ti_qspi_cs_deactivate()
143 	readl(&priv->base->cmd);  in ti_qspi_cs_deactivate()
146 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)  in __ti_qspi_set_mode()  argument
148 	priv->dc = 0;  in __ti_qspi_set_mode()
150 		priv->dc |= QSPI_CKPHA(0);  in __ti_qspi_set_mode()
152 		priv->dc |= QSPI_CKPOL(0);  in __ti_qspi_set_mode()
154 		priv->dc |= QSPI_CSPOL(0);  in __ti_qspi_set_mode()
159 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)  in __ti_qspi_claim_bus()  argument
161 	writel(priv->dc, &priv->base->dc);  in __ti_qspi_claim_bus()
162 	writel(0, &priv->base->cmd);  in __ti_qspi_claim_bus()
163 	writel(0, &priv->base->data);  in __ti_qspi_claim_bus()
165 	priv->dc <<= cs * 8;  in __ti_qspi_claim_bus()
166 	writel(priv->dc, &priv->base->dc);  in __ti_qspi_claim_bus()
171 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)  in __ti_qspi_release_bus()  argument
173 	writel(0, &priv->base->dc);  in __ti_qspi_release_bus()
174 	writel(0, &priv->base->cmd);  in __ti_qspi_release_bus()
175 	writel(0, &priv->base->data);  in __ti_qspi_release_bus()
190 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,  in __ti_qspi_xfer()  argument
202 		writel(MM_SWITCH, &priv->base->memswitch);  in __ti_qspi_xfer()
203 		if (priv->ctrl_mod_mmap)  in __ti_qspi_xfer()
204 			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);  in __ti_qspi_xfer()
207 		writel(~MM_SWITCH, &priv->base->memswitch);  in __ti_qspi_xfer()
208 		if (priv->ctrl_mod_mmap)  in __ti_qspi_xfer()
209 			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);  in __ti_qspi_xfer()
222 	priv->cmd = 0;  in __ti_qspi_xfer()
223 	priv->cmd |= QSPI_WLEN(8);  in __ti_qspi_xfer()
224 	priv->cmd |= QSPI_EN_CS(cs);  in __ti_qspi_xfer()
225 	if (priv->mode & SPI_3WIRE)  in __ti_qspi_xfer()
226 		priv->cmd |= QSPI_3_PIN;  in __ti_qspi_xfer()
227 	priv->cmd |= 0xfff;  in __ti_qspi_xfer()
233 			u32 cmd = priv->cmd;  in __ti_qspi_xfer()
240 				writel(data, &priv->base->data3);  in __ti_qspi_xfer()
242 				writel(data, &priv->base->data2);  in __ti_qspi_xfer()
244 				writel(data, &priv->base->data1);  in __ti_qspi_xfer()
246 				writel(data, &priv->base->data);  in __ti_qspi_xfer()
251 				writeb(*txp, &priv->base->data);  in __ti_qspi_xfer()
255 			      cmd | QSPI_WR_SNGL, priv->dc);  in __ti_qspi_xfer()
256 			writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);  in __ti_qspi_xfer()
257 			status = readl(&priv->base->status);  in __ti_qspi_xfer()
264 				status = readl(&priv->base->status);  in __ti_qspi_xfer()
271 			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);  in __ti_qspi_xfer()
272 			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);  in __ti_qspi_xfer()
273 			status = readl(&priv->base->status);  in __ti_qspi_xfer()
280 				status = readl(&priv->base->status);  in __ti_qspi_xfer()
282 			*rxp++ = readl(&priv->base->data);  in __ti_qspi_xfer()
292 		ti_qspi_cs_deactivate(priv);  in __ti_qspi_xfer()
340 	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);  in spi_cs_deactivate()  local
341 	ti_qspi_cs_deactivate(priv);  in spi_cs_deactivate()
349 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)  in ti_spi_setup_spi_register()  argument
354 	struct spi_slave *slave = &priv->slave;  in ti_spi_setup_spi_register()
367 	writel(memval, &priv->base->setup0);  in ti_spi_setup_spi_register()
373 	struct ti_qspi_priv *priv;  in spi_setup_slave()  local
380 	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);  in spi_setup_slave()
381 	if (!priv) {  in spi_setup_slave()
386 	priv->base = (struct ti_qspi_regs *)QSPI_BASE;  in spi_setup_slave()
387 	priv->mode = mode;  in spi_setup_slave()
389 	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;  in spi_setup_slave()
390 	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;  in spi_setup_slave()
391 	priv->fclk = QSPI_DRA7XX_FCLK;  in spi_setup_slave()
393 	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;  in spi_setup_slave()
394 	priv->fclk = QSPI_FCLK;  in spi_setup_slave()
397 	ti_spi_set_speed(priv, max_hz);  in spi_setup_slave()
400 	ti_spi_setup_spi_register(priv);  in spi_setup_slave()
403 	return &priv->slave;  in spi_setup_slave()
408 	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);  in spi_free_slave()  local
409 	free(priv);  in spi_free_slave()
414 	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);  in spi_claim_bus()  local
416 	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);  in spi_claim_bus()
417 	__ti_qspi_set_mode(priv, priv->mode);  in spi_claim_bus()
418 	return __ti_qspi_claim_bus(priv, priv->slave.cs);  in spi_claim_bus()
422 	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);  in spi_release_bus()  local
424 	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);  in spi_release_bus()
425 	__ti_qspi_release_bus(priv);  in spi_release_bus()
431 	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);  in spi_xfer()  local
434 	      priv->slave.bus, priv->slave.cs, bitlen, flags);  in spi_xfer()
435 	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);  in spi_xfer()
440 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,  in __ti_qspi_setup_memorymap()  argument
448 		writel(0, &priv->base->setup0);  in __ti_qspi_setup_memorymap()
473 	writel(memval, &priv->base->setup0);  in __ti_qspi_setup_memorymap()
479 	struct ti_qspi_priv *priv = dev_get_priv(bus);  in ti_qspi_set_speed()  local
481 	ti_spi_set_speed(priv, max_hz);  in ti_qspi_set_speed()
488 	struct ti_qspi_priv *priv = dev_get_priv(bus);  in ti_qspi_set_mode()  local
489 	return __ti_qspi_set_mode(priv, mode);  in ti_qspi_set_mode()
496 	struct ti_qspi_priv *priv;  in ti_qspi_claim_bus()  local
500 	priv = dev_get_priv(bus);  in ti_qspi_claim_bus()
502 	if (slave_plat->cs > priv->num_cs) {  in ti_qspi_claim_bus()
507 	__ti_qspi_setup_memorymap(priv, slave, true);  in ti_qspi_claim_bus()
509 	return __ti_qspi_claim_bus(priv, slave_plat->cs);  in ti_qspi_claim_bus()
515 	struct ti_qspi_priv *priv;  in ti_qspi_release_bus()  local
519 	priv = dev_get_priv(bus);  in ti_qspi_release_bus()
521 	__ti_qspi_setup_memorymap(priv, slave, false);  in ti_qspi_release_bus()
522 	__ti_qspi_release_bus(priv);  in ti_qspi_release_bus()
531 	struct ti_qspi_priv *priv;  in ti_qspi_xfer()  local
535 	priv = dev_get_priv(bus);  in ti_qspi_xfer()
537 	if (slave->cs > priv->num_cs) {  in ti_qspi_xfer()
542 	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);  in ti_qspi_xfer()
547 	struct ti_qspi_priv *priv = dev_get_priv(bus);  in ti_qspi_probe()  local
549 	priv->fclk = dev_get_driver_data(bus);  in ti_qspi_probe()
595 	struct ti_qspi_priv *priv = dev_get_priv(bus);  in ti_qspi_ofdata_to_platdata()  local
599 	priv->ctrl_mod_mmap = map_syscon_chipselects(bus);  in ti_qspi_ofdata_to_platdata()
600 	priv->base = map_physmem(devfdt_get_addr(bus),  in ti_qspi_ofdata_to_platdata()
602 	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,  in ti_qspi_ofdata_to_platdata()
605 	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);  in ti_qspi_ofdata_to_platdata()
606 	if (priv->max_hz < 0) {  in ti_qspi_ofdata_to_platdata()
610 	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);  in ti_qspi_ofdata_to_platdata()
613 	      (int)priv->base, priv->max_hz);  in ti_qspi_ofdata_to_platdata()
622 	struct ti_qspi_priv *priv = dev_get_priv(bus);  in ti_qspi_child_pre_probe()  local
624 	slave->memory_map = priv->memory_map;  in ti_qspi_child_pre_probe()