History log of /rk3399_rockchip-uboot/drivers/spi/pic32_spi.c (Results 1 – 5 of 5)
Revision Date Author Comments
# 150c5afe 31-May-2017 Simon Glass <sjg@chromium.org>

dm: gpio: Add live tree support

Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix

dm: gpio: Add live tree support

Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: Tom Rini <trini@konsulko.com>

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# 21342d4a 08-Feb-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-dm


# e160f7d4 17-Jan-2017 Simon Glass <sjg@chromium.org>

dm: core: Replace of_offset with accessor

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree,

dm: core: Replace of_offset with accessor

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>

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# b1033500 12-Jun-2016 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-mips


# e19b9004 02-Jun-2016 Purna Chandra Mandal <purna.mandal@microchip.com>

spi: pic32_spi: add SPI master driver for PIC32 SoC.

This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controll

spi: pic32_spi: add SPI master driver for PIC32 SoC.

This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controlling respective pin as gpio ('cs-gpios' property in dt node)
and uses PIO mode for SPI transaction. It is configurable based
on driver-model only.

Cc: Jagan Teki <jteki@openedev.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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