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Searched refs:phy_cfg (Results 1 – 25 of 28) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dddr3.c25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy() argument
33 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
36 tmp &= ~(phy_cfg->pgcr1_mask); in ddr3_init_ddrphy()
37 tmp |= phy_cfg->pgcr1_val; in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
43 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
46 tmp &= ~(phy_cfg->dcr_mask); in ddr3_init_ddrphy()
47 tmp |= phy_cfg->dcr_val; in ddr3_init_ddrphy()
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H A Dddr3_spd.c305 spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; in init_ddr3param()
306 spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK); in init_ddr3param()
307 spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)); in init_ddr3param()
308 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | in init_ddr3param()
310 spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) | in init_ddr3param()
312 spd_cb->phy_cfg.ptr2 = 0; in init_ddr3param()
313 spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) | in init_ddr3param()
315 spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) | in init_ddr3param()
318 spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK; in init_ddr3param()
319 spd_cb->phy_cfg.dcr_val = 1 << 10; in init_ddr3param()
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/rk3399_rockchip-uboot/drivers/usb/phy/
H A Drockchip_usb2_phy.c162 struct rockchip_usb2_phy_cfg *phy_cfg = NULL; in otg_phy_init() local
175 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; in otg_phy_init()
179 if (!phy_cfg) { in otg_phy_init()
185 pdata->priv = phy_cfg; in otg_phy_init()
188 property_enable(pdata, &phy_cfg->siddq, false); in otg_phy_init()
191 property_enable(pdata, &phy_cfg->soft_con, false); in otg_phy_init()
194 property_enable(pdata, &phy_cfg->port_reset, true); in otg_phy_init()
196 property_enable(pdata, &phy_cfg->port_reset, false); in otg_phy_init()
203 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; in otg_phy_off() local
211 property_enable(pdata, &phy_cfg->soft_con, true); in otg_phy_off()
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/rk3399_rockchip-uboot/board/ti/ks2_evm/
H A Dddr3_k2hk.c46 spd_cb.phy_cfg.zq0cr1 |= 0x10000; in ddr3_init()
47 spd_cb.phy_cfg.zq1cr1 |= 0x10000; in ddr3_init()
48 spd_cb.phy_cfg.zq2cr1 |= 0x10000; in ddr3_init()
50 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); in ddr3_init()
56 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); in ddr3_init()
H A Dddr3_k2e.c39 spd_cb.phy_cfg.zq0cr1 |= 0x10000; in ddr3_init()
40 spd_cb.phy_cfg.zq1cr1 |= 0x10000; in ddr3_init()
41 spd_cb.phy_cfg.zq2cr1 |= 0x10000; in ddr3_init()
42 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); in ddr3_init()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip-inno-hdmi-phy.c172 struct phy_config *phy_cfg; member
203 const struct phy_config *phy_cfg);
458 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on() local
464 if (inno->phy_cfg) in inno_hdmi_phy_power_on()
465 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
488 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) in inno_hdmi_phy_power_on()
489 if (tmdsclock <= phy_cfg->tmdsclock) in inno_hdmi_phy_power_on()
492 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) in inno_hdmi_phy_power_on()
497 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
584 const struct phy_config *phy_cfg) in inno_hdmi_phy_rk3228_power_on() argument
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H A Danalogix_dp_reg.c717 union phy_configure_opts phy_cfg; in analogix_dp_set_link_bandwidth() local
723 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_link_bandwidth()
724 phy_cfg.dp.link_rate = in analogix_dp_set_link_bandwidth()
726 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp); in analogix_dp_set_link_bandwidth()
727 phy_cfg.dp.set_lanes = false; in analogix_dp_set_link_bandwidth()
728 phy_cfg.dp.set_rate = true; in analogix_dp_set_link_bandwidth()
729 phy_cfg.dp.set_voltages = false; in analogix_dp_set_link_bandwidth()
730 ret = generic_phy_configure(&dp->phy, &phy_cfg); in analogix_dp_set_link_bandwidth()
756 union phy_configure_opts phy_cfg; in analogix_dp_set_lane_count() local
763 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_lane_count()
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H A Ddw-dp.c596 union phy_configure_opts phy_cfg; in dw_dp_link_train_update_vs_emph() local
605 phy_cfg.dp.voltage[i] = vs[i]; in dw_dp_link_train_update_vs_emph()
606 phy_cfg.dp.pre[i] = pe[i]; in dw_dp_link_train_update_vs_emph()
608 phy_cfg.dp.lanes = lanes; in dw_dp_link_train_update_vs_emph()
609 phy_cfg.dp.link_rate = link->rate / 100; in dw_dp_link_train_update_vs_emph()
610 phy_cfg.dp.set_lanes = false; in dw_dp_link_train_update_vs_emph()
611 phy_cfg.dp.set_rate = false; in dw_dp_link_train_update_vs_emph()
612 phy_cfg.dp.set_voltages = true; in dw_dp_link_train_update_vs_emph()
613 ret = generic_phy_configure(&dp->phy, &phy_cfg); in dw_dp_link_train_update_vs_emph()
630 union phy_configure_opts phy_cfg; in dw_dp_link_configure() local
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/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-usb2.c150 const struct rockchip_usb2phy_cfg *phy_cfg; member
216 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_chg_get_type()
227 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true); in rockchip_chg_get_type()
228 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false); in rockchip_chg_get_type()
234 &rphy->phy_cfg->chg_det.chg_valid); in rockchip_chg_get_type()
237 &rphy->phy_cfg->chg_det.phy_connect); in rockchip_chg_get_type()
250 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true); in rockchip_chg_get_type()
251 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false); in rockchip_chg_get_type()
278 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_usb2phy_check_vbus()
296 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_usb2phy_init()
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H A Dphy-rockchip-inno-usb2.c167 const struct rockchip_usb2phy_cfg *phy_cfg; member
246 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); in rockchip_chg_enable_dcd()
247 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); in rockchip_chg_enable_dcd()
255 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); in rockchip_chg_enable_primary_det()
256 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); in rockchip_chg_enable_primary_det()
264 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); in rockchip_chg_enable_secondary_det()
265 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); in rockchip_chg_enable_secondary_det()
277 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); in rockchip_chg_primary_det_retry()
333 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_chg_get_type()
361 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); in rockchip_chg_get_type()
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H A Dphy-rockchip-naneng-combphy.c387 const struct rockchip_combphy_cfg *phy_cfg; in rockchip_combphy_probe() local
393 phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); in rockchip_combphy_probe()
394 if (!phy_cfg) { in rockchip_combphy_probe()
401 priv->cfg = phy_cfg; in rockchip_combphy_probe()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dddr3.h67 struct ddr3_phy_config phy_cfg; member
81 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
/rk3399_rockchip-uboot/drivers/video/
H A Ddw_hdmi.c317 if (!hdmi->mpll_cfg || !hdmi->phy_cfg) in hdmi_phy_configure()
348 for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++) in hdmi_phy_configure()
349 if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock) in hdmi_phy_configure()
357 hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM); in hdmi_phy_configure()
358 hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL); in hdmi_phy_configure()
359 hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL); in hdmi_phy_configure()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h57 void phy_cfg(void __iomem *phy_base,
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_hdmi.c89 hdmi->phy_cfg = rockchip_phy_config; in rk_hdmi_ofdata_to_platdata()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c170 void phy_cfg(void __iomem *phy_base, in phy_cfg() function
H A Dsdram_rv1108_pctl_phy.c371 static void phy_cfg(struct dram_info *priv, in phy_cfg() function
619 phy_cfg(sdram_priv, params_priv); in rv1108_sdram_init()
H A Dsdram_rk322x.c468 static void phy_cfg(struct chan_info *chan, in phy_cfg() function
700 phy_cfg(&dram->chan[0], sdram_params); in sdram_init()
H A Dsdram_rk3188.c258 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() function
743 phy_cfg(chan, channel, sdram_params); in sdram_init()
H A Dsdram_rk3288.c292 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() function
824 phy_cfg(chan, channel, sdram_params); in sdram_init()
H A Dsdram_rk3328.c369 phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew, in sdram_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c624 static void phy_cfg(struct rk3036_sdram_priv *priv) in phy_cfg() function
757 phy_cfg(&sdram_priv); in sdram_init()
/rk3399_rockchip-uboot/include/
H A Ddw_hdmi.h470 const struct hdmi_phy_config *phy_cfg; member
/rk3399_rockchip-uboot/drivers/pci/
H A Dpcie_dw_rockchip.c709 union phy_configure_opts phy_cfg; in rockchip_pcie_init_port() local
726 phy_cfg.pcie.is_bifurcation = true; in rockchip_pcie_init_port()
727 ret = generic_phy_configure(&priv->phy, &phy_cfg); in rockchip_pcie_init_port()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c247 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() function
723 phy_cfg(chan, channel, sdram_params); in sdram_init()

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