172 	struct phy_config *phy_cfg;  member
203 			const struct phy_config *phy_cfg);
458 	const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;  in inno_hdmi_phy_power_on()  local
464 	if (inno->phy_cfg)  in inno_hdmi_phy_power_on()
465 		phy_cfg = inno->phy_cfg;  in inno_hdmi_phy_power_on()
488 	for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++)  in inno_hdmi_phy_power_on()
489 		if (tmdsclock <= phy_cfg->tmdsclock)  in inno_hdmi_phy_power_on()
492 	if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL)  in inno_hdmi_phy_power_on()
497 		return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);  in inno_hdmi_phy_power_on()
584 			      const struct phy_config *phy_cfg)  in inno_hdmi_phy_rk3228_power_on()  argument
623 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
732 			      const struct phy_config *phy_cfg)  in inno_hdmi_phy_rk3328_power_on()  argument
756 		inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);  in inno_hdmi_phy_rk3328_power_on()
770 	if (phy_cfg->tmdsclock > 340000000) {  in inno_hdmi_phy_rk3328_power_on()
777 	} else if (phy_cfg->tmdsclock > 165000000) {  in inno_hdmi_phy_rk3328_power_on()
791 	val = 47520000000UL / phy_cfg->tmdsclock;  in inno_hdmi_phy_rk3328_power_on()
811 	if (phy_cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3328_power_on()
925 			      const struct phy_config *phy_cfg)  in inno_hdmi_phy_rk3528_power_on()  argument
952 	val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1];  in inno_hdmi_phy_rk3528_power_on()
956 	val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1];  in inno_hdmi_phy_rk3528_power_on()
960 	inno_write(inno, 0xb5, phy_cfg->regs[2]);  in inno_hdmi_phy_rk3528_power_on()
961 	inno_write(inno, 0xb6, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
962 	inno_write(inno, 0xb7, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
963 	inno_write(inno, 0xb8, phy_cfg->regs[3]);  in inno_hdmi_phy_rk3528_power_on()
966 	inno_write(inno, 0xbb, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
967 	inno_write(inno, 0xbc, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
968 	inno_write(inno, 0xbd, phy_cfg->regs[4]);  in inno_hdmi_phy_rk3528_power_on()
989 	inno_write(inno, 0xc7, phy_cfg->regs[5]);  in inno_hdmi_phy_rk3528_power_on()
990 	inno_write(inno, 0xc5, phy_cfg->regs[6]);  in inno_hdmi_phy_rk3528_power_on()
991 	inno_write(inno, 0xc8, phy_cfg->regs[7]);  in inno_hdmi_phy_rk3528_power_on()
992 	inno_write(inno, 0xc9, phy_cfg->regs[8]);  in inno_hdmi_phy_rk3528_power_on()
993 	inno_write(inno, 0xca, phy_cfg->regs[8]);  in inno_hdmi_phy_rk3528_power_on()
994 	inno_write(inno, 0xcb, phy_cfg->regs[8]);  in inno_hdmi_phy_rk3528_power_on()
1002 	if (phy_cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3528_power_on()
1140 			       struct phy_config *phy_cfg,  in inno_hdmi_update_phy_table()  argument
1146 		phy_cfg[i].tmdsclock =  in inno_hdmi_update_phy_table()
1149 		debug("%ld ", phy_cfg[i].tmdsclock);  in inno_hdmi_update_phy_table()
1151 			phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j];  in inno_hdmi_update_phy_table()
1152 			debug("0x%02x ", phy_cfg[i].regs[j]);  in inno_hdmi_update_phy_table()
1161 	phy_cfg[i].tmdsclock = ~0UL;  in inno_hdmi_update_phy_table()
1163 		phy_cfg[i].regs[j] = 0;  in inno_hdmi_update_phy_table()
1276 		inno->phy_cfg = malloc(val + PHY_TAB_LEN);  in inno_hdmi_phy_init()
1277 		if (!inno->phy_cfg) {  in inno_hdmi_phy_init()
1285 						 inno->phy_cfg,  in inno_hdmi_phy_init()
1371 	if (!inno->phy_cfg)  in inno_hdmi_phy_clk_round_rate()
1375 	for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {  in inno_hdmi_phy_clk_round_rate()
1376 		if (inno->phy_cfg[i].tmdsclock >= tmdsclock)  in inno_hdmi_phy_clk_round_rate()
1380 	if (inno->phy_cfg[i].tmdsclock == ~0UL)  in inno_hdmi_phy_clk_round_rate()