xref: /rk3399_rockchip-uboot/board/ti/ks2_evm/ddr3_k2e.c (revision d9a76e77c8c99dc6da98aef94e0a241581d1cbe7)
1a9068479SHao Zhang /*
2a9068479SHao Zhang  * Keystone2: DDR3 initialization
3a9068479SHao Zhang  *
4*d9a76e77SVitaly Andrianov  * (C) Copyright 2014-2015
5a9068479SHao Zhang  *     Texas Instruments Incorporated, <www.ti.com>
6a9068479SHao Zhang  *
7a9068479SHao Zhang  * SPDX-License-Identifier:     GPL-2.0+
8a9068479SHao Zhang  */
9a9068479SHao Zhang 
10a9068479SHao Zhang #include <common.h>
11a9068479SHao Zhang #include "ddr3_cfg.h"
12a9068479SHao Zhang #include <asm/arch/ddr3.h>
13a9068479SHao Zhang 
14a9068479SHao Zhang static struct pll_init_data ddr3_400 = DDR3_PLL_400;
15*d9a76e77SVitaly Andrianov static struct pll_init_data ddr3_333 = DDR3_PLL_333;
16a9068479SHao Zhang 
ddr3_init(void)1766c98a0cSVitaly Andrianov u32 ddr3_init(void)
18a9068479SHao Zhang {
19*d9a76e77SVitaly Andrianov 	struct ddr3_spd_cb spd_cb;
20a9068479SHao Zhang 
21*d9a76e77SVitaly Andrianov 	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
22*d9a76e77SVitaly Andrianov 		printf("Sorry, I don't know how to configure DDR3A.\n"
23*d9a76e77SVitaly Andrianov 		       "Bye :(\n");
24*d9a76e77SVitaly Andrianov 		for (;;)
25*d9a76e77SVitaly Andrianov 			;
26*d9a76e77SVitaly Andrianov 	}
27*d9a76e77SVitaly Andrianov 
28*d9a76e77SVitaly Andrianov 	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
29*d9a76e77SVitaly Andrianov 
30*d9a76e77SVitaly Andrianov 	printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
31*d9a76e77SVitaly Andrianov 	if (spd_cb.ddrspdclock == 1600)
32a9068479SHao Zhang 		init_pll(&ddr3_400);
33*d9a76e77SVitaly Andrianov 	else
34*d9a76e77SVitaly Andrianov 		init_pll(&ddr3_333);
35a9068479SHao Zhang 
36a9068479SHao Zhang 	/* Reset DDR3 PHY after PLL enabled */
37a9068479SHao Zhang 	ddr3_reset_ddrphy();
38a9068479SHao Zhang 
39*d9a76e77SVitaly Andrianov 	spd_cb.phy_cfg.zq0cr1 |= 0x10000;
40*d9a76e77SVitaly Andrianov 	spd_cb.phy_cfg.zq1cr1 |= 0x10000;
41*d9a76e77SVitaly Andrianov 	spd_cb.phy_cfg.zq2cr1 |= 0x10000;
42*d9a76e77SVitaly Andrianov 	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
43*d9a76e77SVitaly Andrianov 	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
44a9068479SHao Zhang 
45*d9a76e77SVitaly Andrianov 	printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
46*d9a76e77SVitaly Andrianov 
47*d9a76e77SVitaly Andrianov 	return (u32)spd_cb.ddr_size_gbyte;
48a9068479SHao Zhang }
49