717 	union phy_configure_opts phy_cfg;  in analogix_dp_set_link_bandwidth()  local
723 	phy_cfg.dp.lanes = dp->link_train.lane_count;  in analogix_dp_set_link_bandwidth()
724 	phy_cfg.dp.link_rate =  in analogix_dp_set_link_bandwidth()
726 	phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);  in analogix_dp_set_link_bandwidth()
727 	phy_cfg.dp.set_lanes = false;  in analogix_dp_set_link_bandwidth()
728 	phy_cfg.dp.set_rate = true;  in analogix_dp_set_link_bandwidth()
729 	phy_cfg.dp.set_voltages = false;  in analogix_dp_set_link_bandwidth()
730 	ret = generic_phy_configure(&dp->phy, &phy_cfg);  in analogix_dp_set_link_bandwidth()
756 	union phy_configure_opts phy_cfg;  in analogix_dp_set_lane_count()  local
763 	phy_cfg.dp.lanes = dp->link_train.lane_count;  in analogix_dp_set_lane_count()
764 	phy_cfg.dp.set_lanes = true;  in analogix_dp_set_lane_count()
765 	phy_cfg.dp.set_rate = false;  in analogix_dp_set_lane_count()
766 	phy_cfg.dp.set_voltages = false;  in analogix_dp_set_lane_count()
767 	ret = generic_phy_configure(&dp->phy, &phy_cfg);  in analogix_dp_set_lane_count()
785 	union phy_configure_opts phy_cfg;  in analogix_dp_set_lane_link_training()  local
801 		phy_cfg.dp.voltage[lane] = vs;  in analogix_dp_set_lane_link_training()
802 		phy_cfg.dp.pre[lane] = pe;  in analogix_dp_set_lane_link_training()
805 	phy_cfg.dp.lanes = dp->link_train.lane_count;  in analogix_dp_set_lane_link_training()
806 	phy_cfg.dp.link_rate =  in analogix_dp_set_lane_link_training()
808 	phy_cfg.dp.set_lanes = false;  in analogix_dp_set_lane_link_training()
809 	phy_cfg.dp.set_rate = false;  in analogix_dp_set_lane_link_training()
810 	phy_cfg.dp.set_voltages = true;  in analogix_dp_set_lane_link_training()
811 	ret = generic_phy_configure(&dp->phy, &phy_cfg);  in analogix_dp_set_lane_link_training()