| /rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/ |
| H A D | clock.c | 43 uint8_t clkfrac, frac; in mxs_get_pclk() local
64 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; in mxs_get_pclk()
66 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_pclk()
93 uint8_t clkfrac, frac; in mxs_get_emiclk() local
107 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; in mxs_get_emiclk()
109 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_emiclk()
124 uint8_t clkfrac, frac; in mxs_get_gpmiclk() local
137 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; in mxs_get_gpmiclk()
139 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_gpmiclk()
|
| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/ |
| H A D | pcc.c | 163 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div) in pcc_clock_div_config() argument
168 (div == 1 && frac != 0)) in pcc_clock_div_config()
186 if (frac) in pcc_clock_div_config()
258 u32 reg, val, rate, frac, div; in pcc_clock_get_rate() local
274 frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET; in pcc_clock_get_rate()
281 rate = rate * (frac + 1) / (div + 1); in pcc_clock_get_rate()
|
| H A D | scg.c | 618 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) in scg_enable_pll_pfd() argument
624 if (frac < 12 || frac > 35) in scg_enable_pll_pfd()
687 reg |= (frac << shift) & mask; in scg_enable_pll_pfd()
|
| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | clk_pic32.c | 175 u64 frac; in pic32_set_refclk() local
187 frac = parent_rate; in pic32_set_refclk()
188 frac <<= 8; in pic32_set_refclk()
189 do_div(frac, rate); in pic32_set_refclk()
190 frac -= (u64)(div << 9); in pic32_set_refclk()
191 trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac; in pic32_set_refclk()
|
| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/ |
| H A D | clock.c | 185 u32 freq, div, frac; in mxc_get_pll_sys_derive() local
212 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> in mxc_get_pll_sys_derive()
219 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> in mxc_get_pll_sys_derive()
227 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> in mxc_get_pll_sys_derive()
234 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> in mxc_get_pll_sys_derive()
242 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> in mxc_get_pll_sys_derive()
249 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> in mxc_get_pll_sys_derive()
257 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >> in mxc_get_pll_sys_derive()
264 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >> in mxc_get_pll_sys_derive()
271 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >> in mxc_get_pll_sys_derive()
[all …]
|
| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 135 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
154 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
161 rate_table->frac = frac_64; in rockchip_pll_clk_set_by_auto()
162 if (rate_table->frac > 0) in rockchip_pll_clk_set_by_auto()
164 debug("frac = %x\n", rate_table->frac); in rockchip_pll_clk_set_by_auto()
307 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
339 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), in rk3036_pll_set_rate()
373 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
405 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> in rk3036_pll_get_rate()
409 u64 frac_rate = p_rate * (u64)frac * KHZ; in rk3036_pll_get_rate()
|
| /rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/ |
| H A D | lowlevel_init.S | 38 #define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \ argument
39 (PLL_CPU_NFRAC(frac) | \
48 #define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \ argument
49 (PLL_DDR_NFRAC(frac) | \
|
| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | stm32mp157a-dk1-u-boot.dtsi | 143 frac = < 0x800 >;
150 frac = < 0x1400 >;
157 frac = < 0x1a04 >;
|
| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_cru.c | 62 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
104 frac = (con2 & PLL_FRAC_MASK) >> PLL_FRAC_SHIFT; in rk628_cru_clk_get_rate_pll()
113 u64 frac_rate = (u64)parent_rate * frac; in rk628_cru_clk_get_rate_pll()
134 u32 frac = 0; in rk628_cru_clk_set_rate_pll() local
224 frac = tmp; in rk628_cru_clk_set_rate_pll()
244 u64 frac_rate = (u64)fin * frac; in rk628_cru_clk_set_rate_pll()
260 rk628_i2c_write(rk628, offset + CRU_CPLL_CON2, PLL_FRAC(frac)); in rk628_cru_clk_set_rate_pll()
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 77 .frac = _frac, \
101 unsigned int frac; member
|
| H A D | cru_rk3036.h | 71 u32 frac; member
|
| H A D | cru_rv1108.h | 59 u32 frac; member
|
| H A D | cru_rv1103b.h | 122 unsigned int frac; member
|
| H A D | cru_rv1106.h | 126 unsigned int frac; member
|
| H A D | cru_rk3506.h | 91 unsigned int frac; member
|
| H A D | cru_rv1126.h | 146 unsigned int frac; member
|
| H A D | cru_px30.h | 122 unsigned int frac; member
|
| H A D | cru_rk3528.h | 112 unsigned int frac; member
|
| H A D | cru_rk3562.h | 147 unsigned int frac; member
|
| H A D | cru_rv1126b.h | 151 unsigned int frac; member
|
| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 95 writel(pll_priv->frac << FRACDIV_SHIFT, in pll_set()
136 rk3308_pll_div.frac = 0x872B02; in rkdclk_init()
146 rk3308_pll_div.frac = 0x24DD2F; in rkdclk_init()
154 rk3308_pll_div.frac = 0x9BA5E3; in rkdclk_init()
190 rk3308_pll_div.frac = 0; in rkdclk_init()
198 rk3308_pll_div.frac = 0; in rkdclk_init()
267 rk3308_pll_div.frac = 0; in rkdclk_init()
330 rk3308_pll_div.frac = 0; in rkdclk_init()
|
| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip-inno-hdmi-phy.c | 891 unsigned long rate, vco, frac; in inno_hdmi_3328_phy_pll_recalc_rate() local
900 frac = inno_read(inno, 0xd3) | in inno_hdmi_3328_phy_pll_recalc_rate()
903 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_3328_phy_pll_recalc_rate()
1101 unsigned long frac; in inno_hdmi_rk3528_phy_pll_recalc_rate() local
1110 frac = inno_read(inno, 0xd3) | in inno_hdmi_rk3528_phy_pll_recalc_rate()
1113 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1127 frac = vco; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1128 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1132 return frac; in inno_hdmi_rk3528_phy_pll_recalc_rate()
|
| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | console_truetype.c | 29 static double frac(double val) in frac() function
215 xpos = frac(VID_TO_PIXEL((double)x)); in console_truetype_putc_xy()
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7ulp/ |
| H A D | pcc.h | 369 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
|
| H A D | scg.h | 328 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
|