1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * Copyright (C) 2015 Freescale Semiconductor, Inc.
3*552a848eSStefano Babic *
4*552a848eSStefano Babic * Author:
5*552a848eSStefano Babic * Peng Fan <Peng.Fan@freescale.com>
6*552a848eSStefano Babic *
7*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
8*552a848eSStefano Babic */
9*552a848eSStefano Babic
10*552a848eSStefano Babic #include <common.h>
11*552a848eSStefano Babic #include <div64.h>
12*552a848eSStefano Babic #include <asm/io.h>
13*552a848eSStefano Babic #include <linux/errno.h>
14*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
15*552a848eSStefano Babic #include <asm/arch/crm_regs.h>
16*552a848eSStefano Babic #include <asm/arch/clock.h>
17*552a848eSStefano Babic #include <asm/arch/sys_proto.h>
18*552a848eSStefano Babic
19*552a848eSStefano Babic struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
20*552a848eSStefano Babic ANATOP_BASE_ADDR;
21*552a848eSStefano Babic struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
22*552a848eSStefano Babic
23*552a848eSStefano Babic #ifdef CONFIG_FSL_ESDHC
24*552a848eSStefano Babic DECLARE_GLOBAL_DATA_PTR;
25*552a848eSStefano Babic #endif
26*552a848eSStefano Babic
get_clocks(void)27*552a848eSStefano Babic int get_clocks(void)
28*552a848eSStefano Babic {
29*552a848eSStefano Babic #ifdef CONFIG_FSL_ESDHC
30*552a848eSStefano Babic #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
31*552a848eSStefano Babic gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
32*552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
33*552a848eSStefano Babic gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
34*552a848eSStefano Babic #else
35*552a848eSStefano Babic gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
36*552a848eSStefano Babic #endif
37*552a848eSStefano Babic #endif
38*552a848eSStefano Babic return 0;
39*552a848eSStefano Babic }
40*552a848eSStefano Babic
get_ahb_clk(void)41*552a848eSStefano Babic u32 get_ahb_clk(void)
42*552a848eSStefano Babic {
43*552a848eSStefano Babic return get_root_clk(AHB_CLK_ROOT);
44*552a848eSStefano Babic }
45*552a848eSStefano Babic
get_ipg_clk(void)46*552a848eSStefano Babic static u32 get_ipg_clk(void)
47*552a848eSStefano Babic {
48*552a848eSStefano Babic /*
49*552a848eSStefano Babic * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
50*552a848eSStefano Babic * each other.
51*552a848eSStefano Babic */
52*552a848eSStefano Babic return get_ahb_clk() / 2;
53*552a848eSStefano Babic }
54*552a848eSStefano Babic
imx_get_uartclk(void)55*552a848eSStefano Babic u32 imx_get_uartclk(void)
56*552a848eSStefano Babic {
57*552a848eSStefano Babic return get_root_clk(UART1_CLK_ROOT);
58*552a848eSStefano Babic }
59*552a848eSStefano Babic
imx_get_fecclk(void)60*552a848eSStefano Babic u32 imx_get_fecclk(void)
61*552a848eSStefano Babic {
62*552a848eSStefano Babic return get_root_clk(ENET_AXI_CLK_ROOT);
63*552a848eSStefano Babic }
64*552a848eSStefano Babic
65*552a848eSStefano Babic #ifdef CONFIG_MXC_OCOTP
enable_ocotp_clk(unsigned char enable)66*552a848eSStefano Babic void enable_ocotp_clk(unsigned char enable)
67*552a848eSStefano Babic {
68*552a848eSStefano Babic clock_enable(CCGR_OCOTP, enable);
69*552a848eSStefano Babic }
70*552a848eSStefano Babic
enable_thermal_clk(void)71*552a848eSStefano Babic void enable_thermal_clk(void)
72*552a848eSStefano Babic {
73*552a848eSStefano Babic enable_ocotp_clk(1);
74*552a848eSStefano Babic }
75*552a848eSStefano Babic #endif
76*552a848eSStefano Babic
enable_usboh3_clk(unsigned char enable)77*552a848eSStefano Babic void enable_usboh3_clk(unsigned char enable)
78*552a848eSStefano Babic {
79*552a848eSStefano Babic u32 target;
80*552a848eSStefano Babic
81*552a848eSStefano Babic if (enable) {
82*552a848eSStefano Babic /* disable the clock gate first */
83*552a848eSStefano Babic clock_enable(CCGR_USB_HSIC, 0);
84*552a848eSStefano Babic
85*552a848eSStefano Babic /* 120Mhz */
86*552a848eSStefano Babic target = CLK_ROOT_ON |
87*552a848eSStefano Babic USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
88*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
89*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
90*552a848eSStefano Babic clock_set_target_val(USB_HSIC_CLK_ROOT, target);
91*552a848eSStefano Babic
92*552a848eSStefano Babic /* enable the clock gate */
93*552a848eSStefano Babic clock_enable(CCGR_USB_CTRL, 1);
94*552a848eSStefano Babic clock_enable(CCGR_USB_HSIC, 1);
95*552a848eSStefano Babic clock_enable(CCGR_USB_PHY1, 1);
96*552a848eSStefano Babic clock_enable(CCGR_USB_PHY2, 1);
97*552a848eSStefano Babic } else {
98*552a848eSStefano Babic clock_enable(CCGR_USB_CTRL, 0);
99*552a848eSStefano Babic clock_enable(CCGR_USB_HSIC, 0);
100*552a848eSStefano Babic clock_enable(CCGR_USB_PHY1, 0);
101*552a848eSStefano Babic clock_enable(CCGR_USB_PHY2, 0);
102*552a848eSStefano Babic }
103*552a848eSStefano Babic }
104*552a848eSStefano Babic
decode_pll(enum pll_clocks pll,u32 infreq)105*552a848eSStefano Babic static u32 decode_pll(enum pll_clocks pll, u32 infreq)
106*552a848eSStefano Babic {
107*552a848eSStefano Babic u32 reg, div_sel;
108*552a848eSStefano Babic u32 num, denom;
109*552a848eSStefano Babic
110*552a848eSStefano Babic /*
111*552a848eSStefano Babic * Alought there are four choices for the bypass src,
112*552a848eSStefano Babic * we choose OSC_24M which is the default set in ROM.
113*552a848eSStefano Babic */
114*552a848eSStefano Babic switch (pll) {
115*552a848eSStefano Babic case PLL_CORE:
116*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_arm);
117*552a848eSStefano Babic
118*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
119*552a848eSStefano Babic return 0;
120*552a848eSStefano Babic
121*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
122*552a848eSStefano Babic return MXC_HCLK;
123*552a848eSStefano Babic
124*552a848eSStefano Babic div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
125*552a848eSStefano Babic CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
126*552a848eSStefano Babic
127*552a848eSStefano Babic return (infreq * div_sel) / 2;
128*552a848eSStefano Babic
129*552a848eSStefano Babic case PLL_SYS:
130*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_480);
131*552a848eSStefano Babic
132*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
133*552a848eSStefano Babic return 0;
134*552a848eSStefano Babic
135*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
136*552a848eSStefano Babic return MXC_HCLK;
137*552a848eSStefano Babic
138*552a848eSStefano Babic if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
139*552a848eSStefano Babic CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
140*552a848eSStefano Babic return 480000000u;
141*552a848eSStefano Babic else
142*552a848eSStefano Babic return 528000000u;
143*552a848eSStefano Babic
144*552a848eSStefano Babic case PLL_ENET:
145*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_enet);
146*552a848eSStefano Babic
147*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
148*552a848eSStefano Babic return 0;
149*552a848eSStefano Babic
150*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
151*552a848eSStefano Babic return MXC_HCLK;
152*552a848eSStefano Babic
153*552a848eSStefano Babic return 1000000000u;
154*552a848eSStefano Babic
155*552a848eSStefano Babic case PLL_DDR:
156*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_ddr);
157*552a848eSStefano Babic
158*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
159*552a848eSStefano Babic return 0;
160*552a848eSStefano Babic
161*552a848eSStefano Babic num = ccm_anatop->pll_ddr_num;
162*552a848eSStefano Babic denom = ccm_anatop->pll_ddr_denom;
163*552a848eSStefano Babic
164*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
165*552a848eSStefano Babic return MXC_HCLK;
166*552a848eSStefano Babic
167*552a848eSStefano Babic div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
168*552a848eSStefano Babic CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
169*552a848eSStefano Babic
170*552a848eSStefano Babic return infreq * (div_sel + num / denom);
171*552a848eSStefano Babic
172*552a848eSStefano Babic case PLL_USB:
173*552a848eSStefano Babic return 480000000u;
174*552a848eSStefano Babic
175*552a848eSStefano Babic default:
176*552a848eSStefano Babic printf("Unsupported pll clocks %d\n", pll);
177*552a848eSStefano Babic break;
178*552a848eSStefano Babic }
179*552a848eSStefano Babic
180*552a848eSStefano Babic return 0;
181*552a848eSStefano Babic }
182*552a848eSStefano Babic
mxc_get_pll_sys_derive(int derive)183*552a848eSStefano Babic static u32 mxc_get_pll_sys_derive(int derive)
184*552a848eSStefano Babic {
185*552a848eSStefano Babic u32 freq, div, frac;
186*552a848eSStefano Babic u32 reg;
187*552a848eSStefano Babic
188*552a848eSStefano Babic div = 1;
189*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_480);
190*552a848eSStefano Babic freq = decode_pll(PLL_SYS, MXC_HCLK);
191*552a848eSStefano Babic
192*552a848eSStefano Babic switch (derive) {
193*552a848eSStefano Babic case PLL_SYS_MAIN_480M_CLK:
194*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
195*552a848eSStefano Babic return 0;
196*552a848eSStefano Babic else
197*552a848eSStefano Babic return freq;
198*552a848eSStefano Babic case PLL_SYS_MAIN_240M_CLK:
199*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
200*552a848eSStefano Babic return 0;
201*552a848eSStefano Babic else
202*552a848eSStefano Babic return freq / 2;
203*552a848eSStefano Babic case PLL_SYS_MAIN_120M_CLK:
204*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
205*552a848eSStefano Babic return 0;
206*552a848eSStefano Babic else
207*552a848eSStefano Babic return freq / 4;
208*552a848eSStefano Babic case PLL_SYS_PFD0_392M_CLK:
209*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
210*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
211*552a848eSStefano Babic return 0;
212*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
213*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
214*552a848eSStefano Babic break;
215*552a848eSStefano Babic case PLL_SYS_PFD0_196M_CLK:
216*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
217*552a848eSStefano Babic return 0;
218*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
219*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
220*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
221*552a848eSStefano Babic div = 2;
222*552a848eSStefano Babic break;
223*552a848eSStefano Babic case PLL_SYS_PFD1_332M_CLK:
224*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
225*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
226*552a848eSStefano Babic return 0;
227*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
228*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
229*552a848eSStefano Babic break;
230*552a848eSStefano Babic case PLL_SYS_PFD1_166M_CLK:
231*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
232*552a848eSStefano Babic return 0;
233*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
234*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
235*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
236*552a848eSStefano Babic div = 2;
237*552a848eSStefano Babic break;
238*552a848eSStefano Babic case PLL_SYS_PFD2_270M_CLK:
239*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
240*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
241*552a848eSStefano Babic return 0;
242*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
243*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
244*552a848eSStefano Babic break;
245*552a848eSStefano Babic case PLL_SYS_PFD2_135M_CLK:
246*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
247*552a848eSStefano Babic return 0;
248*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
249*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
250*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
251*552a848eSStefano Babic div = 2;
252*552a848eSStefano Babic break;
253*552a848eSStefano Babic case PLL_SYS_PFD3_CLK:
254*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480a);
255*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
256*552a848eSStefano Babic return 0;
257*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
258*552a848eSStefano Babic CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
259*552a848eSStefano Babic break;
260*552a848eSStefano Babic case PLL_SYS_PFD4_CLK:
261*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480b);
262*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
263*552a848eSStefano Babic return 0;
264*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
265*552a848eSStefano Babic CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
266*552a848eSStefano Babic break;
267*552a848eSStefano Babic case PLL_SYS_PFD5_CLK:
268*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480b);
269*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
270*552a848eSStefano Babic return 0;
271*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
272*552a848eSStefano Babic CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
273*552a848eSStefano Babic break;
274*552a848eSStefano Babic case PLL_SYS_PFD6_CLK:
275*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480b);
276*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
277*552a848eSStefano Babic return 0;
278*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
279*552a848eSStefano Babic CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
280*552a848eSStefano Babic break;
281*552a848eSStefano Babic case PLL_SYS_PFD7_CLK:
282*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480b);
283*552a848eSStefano Babic if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
284*552a848eSStefano Babic return 0;
285*552a848eSStefano Babic frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
286*552a848eSStefano Babic CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
287*552a848eSStefano Babic break;
288*552a848eSStefano Babic default:
289*552a848eSStefano Babic printf("Error derived pll_sys clock %d\n", derive);
290*552a848eSStefano Babic return 0;
291*552a848eSStefano Babic }
292*552a848eSStefano Babic
293*552a848eSStefano Babic return ((freq / frac) * 18) / div;
294*552a848eSStefano Babic }
295*552a848eSStefano Babic
mxc_get_pll_enet_derive(int derive)296*552a848eSStefano Babic static u32 mxc_get_pll_enet_derive(int derive)
297*552a848eSStefano Babic {
298*552a848eSStefano Babic u32 freq, reg;
299*552a848eSStefano Babic
300*552a848eSStefano Babic freq = decode_pll(PLL_ENET, MXC_HCLK);
301*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_enet);
302*552a848eSStefano Babic
303*552a848eSStefano Babic switch (derive) {
304*552a848eSStefano Babic case PLL_ENET_MAIN_500M_CLK:
305*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
306*552a848eSStefano Babic return freq / 2;
307*552a848eSStefano Babic break;
308*552a848eSStefano Babic case PLL_ENET_MAIN_250M_CLK:
309*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
310*552a848eSStefano Babic return freq / 4;
311*552a848eSStefano Babic break;
312*552a848eSStefano Babic case PLL_ENET_MAIN_125M_CLK:
313*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
314*552a848eSStefano Babic return freq / 8;
315*552a848eSStefano Babic break;
316*552a848eSStefano Babic case PLL_ENET_MAIN_100M_CLK:
317*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
318*552a848eSStefano Babic return freq / 10;
319*552a848eSStefano Babic break;
320*552a848eSStefano Babic case PLL_ENET_MAIN_50M_CLK:
321*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
322*552a848eSStefano Babic return freq / 20;
323*552a848eSStefano Babic break;
324*552a848eSStefano Babic case PLL_ENET_MAIN_40M_CLK:
325*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
326*552a848eSStefano Babic return freq / 25;
327*552a848eSStefano Babic break;
328*552a848eSStefano Babic case PLL_ENET_MAIN_25M_CLK:
329*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
330*552a848eSStefano Babic return freq / 40;
331*552a848eSStefano Babic break;
332*552a848eSStefano Babic default:
333*552a848eSStefano Babic printf("Error derived pll_enet clock %d\n", derive);
334*552a848eSStefano Babic break;
335*552a848eSStefano Babic }
336*552a848eSStefano Babic
337*552a848eSStefano Babic return 0;
338*552a848eSStefano Babic }
339*552a848eSStefano Babic
mxc_get_pll_ddr_derive(int derive)340*552a848eSStefano Babic static u32 mxc_get_pll_ddr_derive(int derive)
341*552a848eSStefano Babic {
342*552a848eSStefano Babic u32 freq, reg;
343*552a848eSStefano Babic
344*552a848eSStefano Babic freq = decode_pll(PLL_DDR, MXC_HCLK);
345*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_ddr);
346*552a848eSStefano Babic
347*552a848eSStefano Babic switch (derive) {
348*552a848eSStefano Babic case PLL_DRAM_MAIN_1066M_CLK:
349*552a848eSStefano Babic return freq;
350*552a848eSStefano Babic case PLL_DRAM_MAIN_533M_CLK:
351*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
352*552a848eSStefano Babic return freq / 2;
353*552a848eSStefano Babic break;
354*552a848eSStefano Babic default:
355*552a848eSStefano Babic printf("Error derived pll_ddr clock %d\n", derive);
356*552a848eSStefano Babic break;
357*552a848eSStefano Babic }
358*552a848eSStefano Babic
359*552a848eSStefano Babic return 0;
360*552a848eSStefano Babic }
361*552a848eSStefano Babic
mxc_get_pll_derive(enum pll_clocks pll,int derive)362*552a848eSStefano Babic static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
363*552a848eSStefano Babic {
364*552a848eSStefano Babic switch (pll) {
365*552a848eSStefano Babic case PLL_SYS:
366*552a848eSStefano Babic return mxc_get_pll_sys_derive(derive);
367*552a848eSStefano Babic case PLL_ENET:
368*552a848eSStefano Babic return mxc_get_pll_enet_derive(derive);
369*552a848eSStefano Babic case PLL_DDR:
370*552a848eSStefano Babic return mxc_get_pll_ddr_derive(derive);
371*552a848eSStefano Babic default:
372*552a848eSStefano Babic printf("Error pll.\n");
373*552a848eSStefano Babic return 0;
374*552a848eSStefano Babic }
375*552a848eSStefano Babic }
376*552a848eSStefano Babic
get_root_src_clk(enum clk_root_src root_src)377*552a848eSStefano Babic static u32 get_root_src_clk(enum clk_root_src root_src)
378*552a848eSStefano Babic {
379*552a848eSStefano Babic switch (root_src) {
380*552a848eSStefano Babic case OSC_24M_CLK:
381*552a848eSStefano Babic return 24000000u;
382*552a848eSStefano Babic case PLL_ARM_MAIN_800M_CLK:
383*552a848eSStefano Babic return decode_pll(PLL_CORE, MXC_HCLK);
384*552a848eSStefano Babic
385*552a848eSStefano Babic case PLL_SYS_MAIN_480M_CLK:
386*552a848eSStefano Babic case PLL_SYS_MAIN_240M_CLK:
387*552a848eSStefano Babic case PLL_SYS_MAIN_120M_CLK:
388*552a848eSStefano Babic case PLL_SYS_PFD0_392M_CLK:
389*552a848eSStefano Babic case PLL_SYS_PFD0_196M_CLK:
390*552a848eSStefano Babic case PLL_SYS_PFD1_332M_CLK:
391*552a848eSStefano Babic case PLL_SYS_PFD1_166M_CLK:
392*552a848eSStefano Babic case PLL_SYS_PFD2_270M_CLK:
393*552a848eSStefano Babic case PLL_SYS_PFD2_135M_CLK:
394*552a848eSStefano Babic case PLL_SYS_PFD3_CLK:
395*552a848eSStefano Babic case PLL_SYS_PFD4_CLK:
396*552a848eSStefano Babic case PLL_SYS_PFD5_CLK:
397*552a848eSStefano Babic case PLL_SYS_PFD6_CLK:
398*552a848eSStefano Babic case PLL_SYS_PFD7_CLK:
399*552a848eSStefano Babic return mxc_get_pll_derive(PLL_SYS, root_src);
400*552a848eSStefano Babic
401*552a848eSStefano Babic case PLL_ENET_MAIN_500M_CLK:
402*552a848eSStefano Babic case PLL_ENET_MAIN_250M_CLK:
403*552a848eSStefano Babic case PLL_ENET_MAIN_125M_CLK:
404*552a848eSStefano Babic case PLL_ENET_MAIN_100M_CLK:
405*552a848eSStefano Babic case PLL_ENET_MAIN_50M_CLK:
406*552a848eSStefano Babic case PLL_ENET_MAIN_40M_CLK:
407*552a848eSStefano Babic case PLL_ENET_MAIN_25M_CLK:
408*552a848eSStefano Babic return mxc_get_pll_derive(PLL_ENET, root_src);
409*552a848eSStefano Babic
410*552a848eSStefano Babic case PLL_DRAM_MAIN_1066M_CLK:
411*552a848eSStefano Babic case PLL_DRAM_MAIN_533M_CLK:
412*552a848eSStefano Babic return mxc_get_pll_derive(PLL_DDR, root_src);
413*552a848eSStefano Babic
414*552a848eSStefano Babic case PLL_AUDIO_MAIN_CLK:
415*552a848eSStefano Babic return decode_pll(PLL_AUDIO, MXC_HCLK);
416*552a848eSStefano Babic case PLL_VIDEO_MAIN_CLK:
417*552a848eSStefano Babic return decode_pll(PLL_VIDEO, MXC_HCLK);
418*552a848eSStefano Babic
419*552a848eSStefano Babic case PLL_USB_MAIN_480M_CLK:
420*552a848eSStefano Babic return decode_pll(PLL_USB, MXC_HCLK);
421*552a848eSStefano Babic
422*552a848eSStefano Babic case REF_1M_CLK:
423*552a848eSStefano Babic return 1000000;
424*552a848eSStefano Babic case OSC_32K_CLK:
425*552a848eSStefano Babic return MXC_CLK32;
426*552a848eSStefano Babic
427*552a848eSStefano Babic case EXT_CLK_1:
428*552a848eSStefano Babic case EXT_CLK_2:
429*552a848eSStefano Babic case EXT_CLK_3:
430*552a848eSStefano Babic case EXT_CLK_4:
431*552a848eSStefano Babic printf("No EXT CLK supported??\n");
432*552a848eSStefano Babic break;
433*552a848eSStefano Babic };
434*552a848eSStefano Babic
435*552a848eSStefano Babic return 0;
436*552a848eSStefano Babic }
437*552a848eSStefano Babic
get_root_clk(enum clk_root_index clock_id)438*552a848eSStefano Babic u32 get_root_clk(enum clk_root_index clock_id)
439*552a848eSStefano Babic {
440*552a848eSStefano Babic enum clk_root_src root_src;
441*552a848eSStefano Babic u32 post_podf, pre_podf, auto_podf, root_src_clk;
442*552a848eSStefano Babic int auto_en;
443*552a848eSStefano Babic
444*552a848eSStefano Babic if (clock_root_enabled(clock_id) <= 0)
445*552a848eSStefano Babic return 0;
446*552a848eSStefano Babic
447*552a848eSStefano Babic if (clock_get_prediv(clock_id, &pre_podf) < 0)
448*552a848eSStefano Babic return 0;
449*552a848eSStefano Babic
450*552a848eSStefano Babic if (clock_get_postdiv(clock_id, &post_podf) < 0)
451*552a848eSStefano Babic return 0;
452*552a848eSStefano Babic
453*552a848eSStefano Babic if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
454*552a848eSStefano Babic return 0;
455*552a848eSStefano Babic
456*552a848eSStefano Babic if (auto_en == 0)
457*552a848eSStefano Babic auto_podf = 0;
458*552a848eSStefano Babic
459*552a848eSStefano Babic if (clock_get_src(clock_id, &root_src) < 0)
460*552a848eSStefano Babic return 0;
461*552a848eSStefano Babic
462*552a848eSStefano Babic root_src_clk = get_root_src_clk(root_src);
463*552a848eSStefano Babic
464*552a848eSStefano Babic /*
465*552a848eSStefano Babic * bypass clk is ignored.
466*552a848eSStefano Babic */
467*552a848eSStefano Babic
468*552a848eSStefano Babic return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
469*552a848eSStefano Babic (auto_podf + 1);
470*552a848eSStefano Babic }
471*552a848eSStefano Babic
get_ddrc_clk(void)472*552a848eSStefano Babic static u32 get_ddrc_clk(void)
473*552a848eSStefano Babic {
474*552a848eSStefano Babic u32 reg, freq;
475*552a848eSStefano Babic enum root_post_div post_div;
476*552a848eSStefano Babic
477*552a848eSStefano Babic reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
478*552a848eSStefano Babic if (reg & CLK_ROOT_MUX_MASK)
479*552a848eSStefano Babic /* DRAM_ALT_CLK_ROOT */
480*552a848eSStefano Babic freq = get_root_clk(DRAM_ALT_CLK_ROOT);
481*552a848eSStefano Babic else
482*552a848eSStefano Babic /* PLL_DRAM_MAIN_1066M_CLK */
483*552a848eSStefano Babic freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
484*552a848eSStefano Babic
485*552a848eSStefano Babic post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
486*552a848eSStefano Babic
487*552a848eSStefano Babic return freq / (post_div + 1) / 2;
488*552a848eSStefano Babic }
489*552a848eSStefano Babic
mxc_get_clock(enum mxc_clock clk)490*552a848eSStefano Babic unsigned int mxc_get_clock(enum mxc_clock clk)
491*552a848eSStefano Babic {
492*552a848eSStefano Babic switch (clk) {
493*552a848eSStefano Babic case MXC_ARM_CLK:
494*552a848eSStefano Babic return get_root_clk(ARM_A7_CLK_ROOT);
495*552a848eSStefano Babic case MXC_AXI_CLK:
496*552a848eSStefano Babic return get_root_clk(MAIN_AXI_CLK_ROOT);
497*552a848eSStefano Babic case MXC_AHB_CLK:
498*552a848eSStefano Babic return get_root_clk(AHB_CLK_ROOT);
499*552a848eSStefano Babic case MXC_IPG_CLK:
500*552a848eSStefano Babic return get_ipg_clk();
501*552a848eSStefano Babic case MXC_I2C_CLK:
502*552a848eSStefano Babic return get_root_clk(I2C1_CLK_ROOT);
503*552a848eSStefano Babic case MXC_UART_CLK:
504*552a848eSStefano Babic return get_root_clk(UART1_CLK_ROOT);
505*552a848eSStefano Babic case MXC_CSPI_CLK:
506*552a848eSStefano Babic return get_root_clk(ECSPI1_CLK_ROOT);
507*552a848eSStefano Babic case MXC_DDR_CLK:
508*552a848eSStefano Babic return get_ddrc_clk();
509*552a848eSStefano Babic case MXC_ESDHC_CLK:
510*552a848eSStefano Babic return get_root_clk(USDHC1_CLK_ROOT);
511*552a848eSStefano Babic case MXC_ESDHC2_CLK:
512*552a848eSStefano Babic return get_root_clk(USDHC2_CLK_ROOT);
513*552a848eSStefano Babic case MXC_ESDHC3_CLK:
514*552a848eSStefano Babic return get_root_clk(USDHC3_CLK_ROOT);
515*552a848eSStefano Babic default:
516*552a848eSStefano Babic printf("Unsupported mxc_clock %d\n", clk);
517*552a848eSStefano Babic break;
518*552a848eSStefano Babic }
519*552a848eSStefano Babic
520*552a848eSStefano Babic return 0;
521*552a848eSStefano Babic }
522*552a848eSStefano Babic
523*552a848eSStefano Babic #ifdef CONFIG_SYS_I2C_MXC
524*552a848eSStefano Babic /* i2c_num can be 0 - 3 */
enable_i2c_clk(unsigned char enable,unsigned i2c_num)525*552a848eSStefano Babic int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
526*552a848eSStefano Babic {
527*552a848eSStefano Babic u32 target;
528*552a848eSStefano Babic
529*552a848eSStefano Babic if (i2c_num >= 4)
530*552a848eSStefano Babic return -EINVAL;
531*552a848eSStefano Babic
532*552a848eSStefano Babic if (enable) {
533*552a848eSStefano Babic clock_enable(CCGR_I2C1 + i2c_num, 0);
534*552a848eSStefano Babic
535*552a848eSStefano Babic /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
536*552a848eSStefano Babic
537*552a848eSStefano Babic target = CLK_ROOT_ON |
538*552a848eSStefano Babic I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
539*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
540*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
541*552a848eSStefano Babic clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
542*552a848eSStefano Babic
543*552a848eSStefano Babic clock_enable(CCGR_I2C1 + i2c_num, 1);
544*552a848eSStefano Babic } else {
545*552a848eSStefano Babic clock_enable(CCGR_I2C1 + i2c_num, 0);
546*552a848eSStefano Babic }
547*552a848eSStefano Babic
548*552a848eSStefano Babic return 0;
549*552a848eSStefano Babic }
550*552a848eSStefano Babic #endif
551*552a848eSStefano Babic
init_clk_esdhc(void)552*552a848eSStefano Babic static void init_clk_esdhc(void)
553*552a848eSStefano Babic {
554*552a848eSStefano Babic u32 target;
555*552a848eSStefano Babic
556*552a848eSStefano Babic /* disable the clock gate first */
557*552a848eSStefano Babic clock_enable(CCGR_USDHC1, 0);
558*552a848eSStefano Babic clock_enable(CCGR_USDHC2, 0);
559*552a848eSStefano Babic clock_enable(CCGR_USDHC3, 0);
560*552a848eSStefano Babic
561*552a848eSStefano Babic /* 196: 392/2 */
562*552a848eSStefano Babic target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
563*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
564*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
565*552a848eSStefano Babic clock_set_target_val(USDHC1_CLK_ROOT, target);
566*552a848eSStefano Babic
567*552a848eSStefano Babic target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
568*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
569*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
570*552a848eSStefano Babic clock_set_target_val(USDHC2_CLK_ROOT, target);
571*552a848eSStefano Babic
572*552a848eSStefano Babic target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
573*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
574*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
575*552a848eSStefano Babic clock_set_target_val(USDHC3_CLK_ROOT, target);
576*552a848eSStefano Babic
577*552a848eSStefano Babic /* enable the clock gate */
578*552a848eSStefano Babic clock_enable(CCGR_USDHC1, 1);
579*552a848eSStefano Babic clock_enable(CCGR_USDHC2, 1);
580*552a848eSStefano Babic clock_enable(CCGR_USDHC3, 1);
581*552a848eSStefano Babic }
582*552a848eSStefano Babic
init_clk_uart(void)583*552a848eSStefano Babic static void init_clk_uart(void)
584*552a848eSStefano Babic {
585*552a848eSStefano Babic u32 target;
586*552a848eSStefano Babic
587*552a848eSStefano Babic /* disable the clock gate first */
588*552a848eSStefano Babic clock_enable(CCGR_UART1, 0);
589*552a848eSStefano Babic clock_enable(CCGR_UART2, 0);
590*552a848eSStefano Babic clock_enable(CCGR_UART3, 0);
591*552a848eSStefano Babic clock_enable(CCGR_UART4, 0);
592*552a848eSStefano Babic clock_enable(CCGR_UART5, 0);
593*552a848eSStefano Babic clock_enable(CCGR_UART6, 0);
594*552a848eSStefano Babic clock_enable(CCGR_UART7, 0);
595*552a848eSStefano Babic
596*552a848eSStefano Babic /* 24Mhz */
597*552a848eSStefano Babic target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
598*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
599*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
600*552a848eSStefano Babic clock_set_target_val(UART1_CLK_ROOT, target);
601*552a848eSStefano Babic
602*552a848eSStefano Babic target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
603*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
604*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
605*552a848eSStefano Babic clock_set_target_val(UART2_CLK_ROOT, target);
606*552a848eSStefano Babic
607*552a848eSStefano Babic target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
608*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
609*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
610*552a848eSStefano Babic clock_set_target_val(UART3_CLK_ROOT, target);
611*552a848eSStefano Babic
612*552a848eSStefano Babic target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
613*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
614*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
615*552a848eSStefano Babic clock_set_target_val(UART4_CLK_ROOT, target);
616*552a848eSStefano Babic
617*552a848eSStefano Babic target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
618*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
619*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
620*552a848eSStefano Babic clock_set_target_val(UART5_CLK_ROOT, target);
621*552a848eSStefano Babic
622*552a848eSStefano Babic target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
623*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
624*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
625*552a848eSStefano Babic clock_set_target_val(UART6_CLK_ROOT, target);
626*552a848eSStefano Babic
627*552a848eSStefano Babic target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
628*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
629*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
630*552a848eSStefano Babic clock_set_target_val(UART7_CLK_ROOT, target);
631*552a848eSStefano Babic
632*552a848eSStefano Babic /* enable the clock gate */
633*552a848eSStefano Babic clock_enable(CCGR_UART1, 1);
634*552a848eSStefano Babic clock_enable(CCGR_UART2, 1);
635*552a848eSStefano Babic clock_enable(CCGR_UART3, 1);
636*552a848eSStefano Babic clock_enable(CCGR_UART4, 1);
637*552a848eSStefano Babic clock_enable(CCGR_UART5, 1);
638*552a848eSStefano Babic clock_enable(CCGR_UART6, 1);
639*552a848eSStefano Babic clock_enable(CCGR_UART7, 1);
640*552a848eSStefano Babic }
641*552a848eSStefano Babic
init_clk_weim(void)642*552a848eSStefano Babic static void init_clk_weim(void)
643*552a848eSStefano Babic {
644*552a848eSStefano Babic u32 target;
645*552a848eSStefano Babic
646*552a848eSStefano Babic /* disable the clock gate first */
647*552a848eSStefano Babic clock_enable(CCGR_WEIM, 0);
648*552a848eSStefano Babic
649*552a848eSStefano Babic /* 120Mhz */
650*552a848eSStefano Babic target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
651*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
652*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
653*552a848eSStefano Babic clock_set_target_val(EIM_CLK_ROOT, target);
654*552a848eSStefano Babic
655*552a848eSStefano Babic /* enable the clock gate */
656*552a848eSStefano Babic clock_enable(CCGR_WEIM, 1);
657*552a848eSStefano Babic }
658*552a848eSStefano Babic
init_clk_ecspi(void)659*552a848eSStefano Babic static void init_clk_ecspi(void)
660*552a848eSStefano Babic {
661*552a848eSStefano Babic u32 target;
662*552a848eSStefano Babic
663*552a848eSStefano Babic /* disable the clock gate first */
664*552a848eSStefano Babic clock_enable(CCGR_ECSPI1, 0);
665*552a848eSStefano Babic clock_enable(CCGR_ECSPI2, 0);
666*552a848eSStefano Babic clock_enable(CCGR_ECSPI3, 0);
667*552a848eSStefano Babic clock_enable(CCGR_ECSPI4, 0);
668*552a848eSStefano Babic
669*552a848eSStefano Babic /* 60Mhz: 240/4 */
670*552a848eSStefano Babic target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
671*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
672*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
673*552a848eSStefano Babic clock_set_target_val(ECSPI1_CLK_ROOT, target);
674*552a848eSStefano Babic
675*552a848eSStefano Babic target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
676*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
677*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
678*552a848eSStefano Babic clock_set_target_val(ECSPI2_CLK_ROOT, target);
679*552a848eSStefano Babic
680*552a848eSStefano Babic target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
681*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
682*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
683*552a848eSStefano Babic clock_set_target_val(ECSPI3_CLK_ROOT, target);
684*552a848eSStefano Babic
685*552a848eSStefano Babic target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
686*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
687*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
688*552a848eSStefano Babic clock_set_target_val(ECSPI4_CLK_ROOT, target);
689*552a848eSStefano Babic
690*552a848eSStefano Babic /* enable the clock gate */
691*552a848eSStefano Babic clock_enable(CCGR_ECSPI1, 1);
692*552a848eSStefano Babic clock_enable(CCGR_ECSPI2, 1);
693*552a848eSStefano Babic clock_enable(CCGR_ECSPI3, 1);
694*552a848eSStefano Babic clock_enable(CCGR_ECSPI4, 1);
695*552a848eSStefano Babic }
696*552a848eSStefano Babic
init_clk_wdog(void)697*552a848eSStefano Babic static void init_clk_wdog(void)
698*552a848eSStefano Babic {
699*552a848eSStefano Babic u32 target;
700*552a848eSStefano Babic
701*552a848eSStefano Babic /* disable the clock gate first */
702*552a848eSStefano Babic clock_enable(CCGR_WDOG1, 0);
703*552a848eSStefano Babic clock_enable(CCGR_WDOG2, 0);
704*552a848eSStefano Babic clock_enable(CCGR_WDOG3, 0);
705*552a848eSStefano Babic clock_enable(CCGR_WDOG4, 0);
706*552a848eSStefano Babic
707*552a848eSStefano Babic /* 24Mhz */
708*552a848eSStefano Babic target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
709*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
710*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
711*552a848eSStefano Babic clock_set_target_val(WDOG_CLK_ROOT, target);
712*552a848eSStefano Babic
713*552a848eSStefano Babic /* enable the clock gate */
714*552a848eSStefano Babic clock_enable(CCGR_WDOG1, 1);
715*552a848eSStefano Babic clock_enable(CCGR_WDOG2, 1);
716*552a848eSStefano Babic clock_enable(CCGR_WDOG3, 1);
717*552a848eSStefano Babic clock_enable(CCGR_WDOG4, 1);
718*552a848eSStefano Babic }
719*552a848eSStefano Babic
720*552a848eSStefano Babic #ifdef CONFIG_MXC_EPDC
init_clk_epdc(void)721*552a848eSStefano Babic static void init_clk_epdc(void)
722*552a848eSStefano Babic {
723*552a848eSStefano Babic u32 target;
724*552a848eSStefano Babic
725*552a848eSStefano Babic /* disable the clock gate first */
726*552a848eSStefano Babic clock_enable(CCGR_EPDC, 0);
727*552a848eSStefano Babic
728*552a848eSStefano Babic /* 24Mhz */
729*552a848eSStefano Babic target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
730*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
731*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
732*552a848eSStefano Babic clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
733*552a848eSStefano Babic
734*552a848eSStefano Babic /* enable the clock gate */
735*552a848eSStefano Babic clock_enable(CCGR_EPDC, 1);
736*552a848eSStefano Babic }
737*552a848eSStefano Babic #endif
738*552a848eSStefano Babic
enable_pll_enet(void)739*552a848eSStefano Babic static int enable_pll_enet(void)
740*552a848eSStefano Babic {
741*552a848eSStefano Babic u32 reg;
742*552a848eSStefano Babic s32 timeout = 100000;
743*552a848eSStefano Babic
744*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_enet);
745*552a848eSStefano Babic /* If pll_enet powered up, no need to set it again */
746*552a848eSStefano Babic if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
747*552a848eSStefano Babic reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
748*552a848eSStefano Babic writel(reg, &ccm_anatop->pll_enet);
749*552a848eSStefano Babic
750*552a848eSStefano Babic while (timeout--) {
751*552a848eSStefano Babic if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
752*552a848eSStefano Babic break;
753*552a848eSStefano Babic }
754*552a848eSStefano Babic
755*552a848eSStefano Babic if (timeout <= 0) {
756*552a848eSStefano Babic /* If timeout, we set pwdn for pll_enet. */
757*552a848eSStefano Babic reg |= ANADIG_PLL_ENET_PWDN_MASK;
758*552a848eSStefano Babic return -ETIME;
759*552a848eSStefano Babic }
760*552a848eSStefano Babic }
761*552a848eSStefano Babic
762*552a848eSStefano Babic /* Clear bypass */
763*552a848eSStefano Babic writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
764*552a848eSStefano Babic
765*552a848eSStefano Babic writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
766*552a848eSStefano Babic | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
767*552a848eSStefano Babic | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
768*552a848eSStefano Babic | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
769*552a848eSStefano Babic | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
770*552a848eSStefano Babic | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
771*552a848eSStefano Babic | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
772*552a848eSStefano Babic &ccm_anatop->pll_enet_set);
773*552a848eSStefano Babic
774*552a848eSStefano Babic return 0;
775*552a848eSStefano Babic }
enable_pll_video(u32 pll_div,u32 pll_num,u32 pll_denom,u32 post_div)776*552a848eSStefano Babic static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
777*552a848eSStefano Babic u32 post_div)
778*552a848eSStefano Babic {
779*552a848eSStefano Babic u32 reg = 0;
780*552a848eSStefano Babic ulong start;
781*552a848eSStefano Babic
782*552a848eSStefano Babic debug("pll5 div = %d, num = %d, denom = %d\n",
783*552a848eSStefano Babic pll_div, pll_num, pll_denom);
784*552a848eSStefano Babic
785*552a848eSStefano Babic /* Power up PLL5 video and disable its output */
786*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
787*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
788*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
789*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
790*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
791*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
792*552a848eSStefano Babic &ccm_anatop->pll_video_clr);
793*552a848eSStefano Babic
794*552a848eSStefano Babic /* Set div, num and denom */
795*552a848eSStefano Babic switch (post_div) {
796*552a848eSStefano Babic case 1:
797*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
798*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
799*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
800*552a848eSStefano Babic &ccm_anatop->pll_video_set);
801*552a848eSStefano Babic break;
802*552a848eSStefano Babic case 2:
803*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
804*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
805*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
806*552a848eSStefano Babic &ccm_anatop->pll_video_set);
807*552a848eSStefano Babic break;
808*552a848eSStefano Babic case 3:
809*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
810*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
811*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
812*552a848eSStefano Babic &ccm_anatop->pll_video_set);
813*552a848eSStefano Babic break;
814*552a848eSStefano Babic case 4:
815*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
816*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
817*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
818*552a848eSStefano Babic &ccm_anatop->pll_video_set);
819*552a848eSStefano Babic break;
820*552a848eSStefano Babic case 0:
821*552a848eSStefano Babic default:
822*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
823*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
824*552a848eSStefano Babic CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
825*552a848eSStefano Babic &ccm_anatop->pll_video_set);
826*552a848eSStefano Babic break;
827*552a848eSStefano Babic }
828*552a848eSStefano Babic
829*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
830*552a848eSStefano Babic &ccm_anatop->pll_video_num);
831*552a848eSStefano Babic
832*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
833*552a848eSStefano Babic &ccm_anatop->pll_video_denom);
834*552a848eSStefano Babic
835*552a848eSStefano Babic /* Wait PLL5 lock */
836*552a848eSStefano Babic start = get_timer(0); /* Get current timestamp */
837*552a848eSStefano Babic
838*552a848eSStefano Babic do {
839*552a848eSStefano Babic reg = readl(&ccm_anatop->pll_video);
840*552a848eSStefano Babic if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
841*552a848eSStefano Babic /* Enable PLL out */
842*552a848eSStefano Babic writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
843*552a848eSStefano Babic &ccm_anatop->pll_video_set);
844*552a848eSStefano Babic return 0;
845*552a848eSStefano Babic }
846*552a848eSStefano Babic } while (get_timer(0) < (start + 10)); /* Wait 10ms */
847*552a848eSStefano Babic
848*552a848eSStefano Babic printf("Lock PLL5 timeout\n");
849*552a848eSStefano Babic
850*552a848eSStefano Babic return 1;
851*552a848eSStefano Babic }
852*552a848eSStefano Babic
set_clk_qspi(void)853*552a848eSStefano Babic int set_clk_qspi(void)
854*552a848eSStefano Babic {
855*552a848eSStefano Babic u32 target;
856*552a848eSStefano Babic
857*552a848eSStefano Babic /* disable the clock gate first */
858*552a848eSStefano Babic clock_enable(CCGR_QSPI, 0);
859*552a848eSStefano Babic
860*552a848eSStefano Babic /* 49M: 392/2/4 */
861*552a848eSStefano Babic target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
862*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
863*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
864*552a848eSStefano Babic clock_set_target_val(QSPI_CLK_ROOT, target);
865*552a848eSStefano Babic
866*552a848eSStefano Babic /* enable the clock gate */
867*552a848eSStefano Babic clock_enable(CCGR_QSPI, 1);
868*552a848eSStefano Babic
869*552a848eSStefano Babic return 0;
870*552a848eSStefano Babic }
871*552a848eSStefano Babic
set_clk_nand(void)872*552a848eSStefano Babic int set_clk_nand(void)
873*552a848eSStefano Babic {
874*552a848eSStefano Babic u32 target;
875*552a848eSStefano Babic
876*552a848eSStefano Babic /* disable the clock gate first */
877*552a848eSStefano Babic clock_enable(CCGR_RAWNAND, 0);
878*552a848eSStefano Babic
879*552a848eSStefano Babic enable_pll_enet();
880*552a848eSStefano Babic /* 100: 500/5 */
881*552a848eSStefano Babic target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
882*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
883*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
884*552a848eSStefano Babic clock_set_target_val(NAND_CLK_ROOT, target);
885*552a848eSStefano Babic
886*552a848eSStefano Babic /* enable the clock gate */
887*552a848eSStefano Babic clock_enable(CCGR_RAWNAND, 1);
888*552a848eSStefano Babic
889*552a848eSStefano Babic return 0;
890*552a848eSStefano Babic }
891*552a848eSStefano Babic
mxs_set_lcdclk(uint32_t base_addr,uint32_t freq)892*552a848eSStefano Babic void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
893*552a848eSStefano Babic {
894*552a848eSStefano Babic u32 hck = MXC_HCLK/1000;
895*552a848eSStefano Babic u32 min = hck * 27;
896*552a848eSStefano Babic u32 max = hck * 54;
897*552a848eSStefano Babic u32 temp, best = 0;
898*552a848eSStefano Babic u32 i, j, pred = 1, postd = 1;
899*552a848eSStefano Babic u32 pll_div, pll_num, pll_denom, post_div = 0;
900*552a848eSStefano Babic u32 target;
901*552a848eSStefano Babic
902*552a848eSStefano Babic debug("mxs_set_lcdclk, freq = %d\n", freq);
903*552a848eSStefano Babic
904*552a848eSStefano Babic clock_enable(CCGR_LCDIF, 0);
905*552a848eSStefano Babic
906*552a848eSStefano Babic temp = (freq * 8 * 8);
907*552a848eSStefano Babic if (temp < min) {
908*552a848eSStefano Babic for (i = 1; i <= 4; i++) {
909*552a848eSStefano Babic if ((temp * (1 << i)) > min) {
910*552a848eSStefano Babic post_div = i;
911*552a848eSStefano Babic freq = (freq * (1 << i));
912*552a848eSStefano Babic break;
913*552a848eSStefano Babic }
914*552a848eSStefano Babic }
915*552a848eSStefano Babic
916*552a848eSStefano Babic if (5 == i) {
917*552a848eSStefano Babic printf("Fail to set rate to %dkhz", freq);
918*552a848eSStefano Babic return;
919*552a848eSStefano Babic }
920*552a848eSStefano Babic }
921*552a848eSStefano Babic
922*552a848eSStefano Babic for (i = 1; i <= 8; i++) {
923*552a848eSStefano Babic for (j = 1; j <= 8; j++) {
924*552a848eSStefano Babic temp = freq * i * j;
925*552a848eSStefano Babic if (temp > max || temp < min)
926*552a848eSStefano Babic continue;
927*552a848eSStefano Babic
928*552a848eSStefano Babic if (best == 0 || temp < best) {
929*552a848eSStefano Babic best = temp;
930*552a848eSStefano Babic pred = i;
931*552a848eSStefano Babic postd = j;
932*552a848eSStefano Babic }
933*552a848eSStefano Babic }
934*552a848eSStefano Babic }
935*552a848eSStefano Babic
936*552a848eSStefano Babic if (best == 0) {
937*552a848eSStefano Babic printf("Fail to set rate to %dkhz", freq);
938*552a848eSStefano Babic return;
939*552a848eSStefano Babic }
940*552a848eSStefano Babic
941*552a848eSStefano Babic debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
942*552a848eSStefano Babic
943*552a848eSStefano Babic pll_div = best / hck;
944*552a848eSStefano Babic pll_denom = 1000000;
945*552a848eSStefano Babic pll_num = (best - hck * pll_div) * pll_denom / hck;
946*552a848eSStefano Babic
947*552a848eSStefano Babic if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
948*552a848eSStefano Babic return;
949*552a848eSStefano Babic
950*552a848eSStefano Babic target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
951*552a848eSStefano Babic CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
952*552a848eSStefano Babic clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
953*552a848eSStefano Babic
954*552a848eSStefano Babic clock_enable(CCGR_LCDIF, 1);
955*552a848eSStefano Babic }
956*552a848eSStefano Babic
957*552a848eSStefano Babic #ifdef CONFIG_FEC_MXC
set_clk_enet(enum enet_freq type)958*552a848eSStefano Babic int set_clk_enet(enum enet_freq type)
959*552a848eSStefano Babic {
960*552a848eSStefano Babic u32 target;
961*552a848eSStefano Babic int ret;
962*552a848eSStefano Babic u32 enet1_ref, enet2_ref;
963*552a848eSStefano Babic
964*552a848eSStefano Babic /* disable the clock first */
965*552a848eSStefano Babic clock_enable(CCGR_ENET1, 0);
966*552a848eSStefano Babic clock_enable(CCGR_ENET2, 0);
967*552a848eSStefano Babic
968*552a848eSStefano Babic switch (type) {
969*552a848eSStefano Babic case ENET_125MHz:
970*552a848eSStefano Babic enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
971*552a848eSStefano Babic enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
972*552a848eSStefano Babic break;
973*552a848eSStefano Babic case ENET_50MHz:
974*552a848eSStefano Babic enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
975*552a848eSStefano Babic enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
976*552a848eSStefano Babic break;
977*552a848eSStefano Babic case ENET_25MHz:
978*552a848eSStefano Babic enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
979*552a848eSStefano Babic enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
980*552a848eSStefano Babic break;
981*552a848eSStefano Babic default:
982*552a848eSStefano Babic return -EINVAL;
983*552a848eSStefano Babic }
984*552a848eSStefano Babic
985*552a848eSStefano Babic ret = enable_pll_enet();
986*552a848eSStefano Babic if (ret != 0)
987*552a848eSStefano Babic return ret;
988*552a848eSStefano Babic
989*552a848eSStefano Babic /* set enet axi clock 196M: 392/2 */
990*552a848eSStefano Babic target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
991*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
992*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
993*552a848eSStefano Babic clock_set_target_val(ENET_AXI_CLK_ROOT, target);
994*552a848eSStefano Babic
995*552a848eSStefano Babic target = CLK_ROOT_ON | enet1_ref |
996*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
997*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
998*552a848eSStefano Babic clock_set_target_val(ENET1_REF_CLK_ROOT, target);
999*552a848eSStefano Babic
1000*552a848eSStefano Babic target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1001*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1002*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1003*552a848eSStefano Babic clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
1004*552a848eSStefano Babic
1005*552a848eSStefano Babic target = CLK_ROOT_ON | enet2_ref |
1006*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1007*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1008*552a848eSStefano Babic clock_set_target_val(ENET2_REF_CLK_ROOT, target);
1009*552a848eSStefano Babic
1010*552a848eSStefano Babic target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1011*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1012*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1013*552a848eSStefano Babic clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
1014*552a848eSStefano Babic
1015*552a848eSStefano Babic #ifdef CONFIG_FEC_MXC_25M_REF_CLK
1016*552a848eSStefano Babic target = CLK_ROOT_ON |
1017*552a848eSStefano Babic ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
1018*552a848eSStefano Babic CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1019*552a848eSStefano Babic CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1020*552a848eSStefano Babic clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
1021*552a848eSStefano Babic #endif
1022*552a848eSStefano Babic /* enable clock */
1023*552a848eSStefano Babic clock_enable(CCGR_ENET1, 1);
1024*552a848eSStefano Babic clock_enable(CCGR_ENET2, 1);
1025*552a848eSStefano Babic
1026*552a848eSStefano Babic return 0;
1027*552a848eSStefano Babic }
1028*552a848eSStefano Babic #endif
1029*552a848eSStefano Babic
1030*552a848eSStefano Babic /* Configure PLL/PFD freq */
clock_init(void)1031*552a848eSStefano Babic void clock_init(void)
1032*552a848eSStefano Babic {
1033*552a848eSStefano Babic /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
1034*552a848eSStefano Babic * In u-boot, we have to:
1035*552a848eSStefano Babic * 1. Configure PFD3- PFD7 for freq we needed in u-boot
1036*552a848eSStefano Babic * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
1037*552a848eSStefano Babic * interface. The clocks for these peripherals are enabled after this intialization.
1038*552a848eSStefano Babic * 3. Other peripherals with set clock rate interface does not be set in this function.
1039*552a848eSStefano Babic */
1040*552a848eSStefano Babic u32 reg;
1041*552a848eSStefano Babic
1042*552a848eSStefano Babic /*
1043*552a848eSStefano Babic * Configure PFD4 to 392M
1044*552a848eSStefano Babic * 480M * 18 / 0x16 = 392M
1045*552a848eSStefano Babic */
1046*552a848eSStefano Babic reg = readl(&ccm_anatop->pfd_480b);
1047*552a848eSStefano Babic
1048*552a848eSStefano Babic reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
1049*552a848eSStefano Babic CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
1050*552a848eSStefano Babic reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
1051*552a848eSStefano Babic
1052*552a848eSStefano Babic writel(reg, &ccm_anatop->pfd_480b);
1053*552a848eSStefano Babic
1054*552a848eSStefano Babic init_clk_esdhc();
1055*552a848eSStefano Babic init_clk_uart();
1056*552a848eSStefano Babic init_clk_weim();
1057*552a848eSStefano Babic init_clk_ecspi();
1058*552a848eSStefano Babic init_clk_wdog();
1059*552a848eSStefano Babic #ifdef CONFIG_MXC_EPDC
1060*552a848eSStefano Babic init_clk_epdc();
1061*552a848eSStefano Babic #endif
1062*552a848eSStefano Babic
1063*552a848eSStefano Babic enable_usboh3_clk(1);
1064*552a848eSStefano Babic
1065*552a848eSStefano Babic clock_enable(CCGR_SNVS, 1);
1066*552a848eSStefano Babic
1067*552a848eSStefano Babic #ifdef CONFIG_NAND_MXS
1068*552a848eSStefano Babic clock_enable(CCGR_RAWNAND, 1);
1069*552a848eSStefano Babic #endif
1070*552a848eSStefano Babic
1071*552a848eSStefano Babic if (IS_ENABLED(CONFIG_IMX_RDC)) {
1072*552a848eSStefano Babic clock_enable(CCGR_RDC, 1);
1073*552a848eSStefano Babic clock_enable(CCGR_SEMA1, 1);
1074*552a848eSStefano Babic clock_enable(CCGR_SEMA2, 1);
1075*552a848eSStefano Babic }
1076*552a848eSStefano Babic }
1077*552a848eSStefano Babic
1078*552a848eSStefano Babic #ifdef CONFIG_SECURE_BOOT
hab_caam_clock_enable(unsigned char enable)1079*552a848eSStefano Babic void hab_caam_clock_enable(unsigned char enable)
1080*552a848eSStefano Babic {
1081*552a848eSStefano Babic if (enable)
1082*552a848eSStefano Babic clock_enable(CCGR_CAAM, 1);
1083*552a848eSStefano Babic else
1084*552a848eSStefano Babic clock_enable(CCGR_CAAM, 0);
1085*552a848eSStefano Babic }
1086*552a848eSStefano Babic #endif
1087*552a848eSStefano Babic
1088*552a848eSStefano Babic #ifdef CONFIG_MXC_EPDC
epdc_clock_enable(void)1089*552a848eSStefano Babic void epdc_clock_enable(void)
1090*552a848eSStefano Babic {
1091*552a848eSStefano Babic clock_enable(CCGR_EPDC, 1);
1092*552a848eSStefano Babic }
epdc_clock_disable(void)1093*552a848eSStefano Babic void epdc_clock_disable(void)
1094*552a848eSStefano Babic {
1095*552a848eSStefano Babic clock_enable(CCGR_EPDC, 0);
1096*552a848eSStefano Babic }
1097*552a848eSStefano Babic #endif
1098*552a848eSStefano Babic
1099*552a848eSStefano Babic /*
1100*552a848eSStefano Babic * Dump some core clockes.
1101*552a848eSStefano Babic */
do_mx7_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1102*552a848eSStefano Babic int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1103*552a848eSStefano Babic {
1104*552a848eSStefano Babic u32 freq;
1105*552a848eSStefano Babic freq = decode_pll(PLL_CORE, MXC_HCLK);
1106*552a848eSStefano Babic printf("PLL_CORE %8d MHz\n", freq / 1000000);
1107*552a848eSStefano Babic freq = decode_pll(PLL_SYS, MXC_HCLK);
1108*552a848eSStefano Babic printf("PLL_SYS %8d MHz\n", freq / 1000000);
1109*552a848eSStefano Babic freq = decode_pll(PLL_ENET, MXC_HCLK);
1110*552a848eSStefano Babic printf("PLL_NET %8d MHz\n", freq / 1000000);
1111*552a848eSStefano Babic
1112*552a848eSStefano Babic printf("\n");
1113*552a848eSStefano Babic
1114*552a848eSStefano Babic printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1115*552a848eSStefano Babic printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1116*552a848eSStefano Babic #ifdef CONFIG_MXC_SPI
1117*552a848eSStefano Babic printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1118*552a848eSStefano Babic #endif
1119*552a848eSStefano Babic printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1120*552a848eSStefano Babic printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1121*552a848eSStefano Babic printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1122*552a848eSStefano Babic printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1123*552a848eSStefano Babic printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1124*552a848eSStefano Babic printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1125*552a848eSStefano Babic
1126*552a848eSStefano Babic return 0;
1127*552a848eSStefano Babic }
1128*552a848eSStefano Babic
1129*552a848eSStefano Babic U_BOOT_CMD(
1130*552a848eSStefano Babic clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
1131*552a848eSStefano Babic "display clocks",
1132*552a848eSStefano Babic ""
1133*552a848eSStefano Babic );
1134