Searched refs:PPLL (Results 1 – 10 of 10) sorted by relevance
| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3588.c | 66 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
1550 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_get_rate()
1551 priv->cru, PPLL); in rk3588_clk_get_rate()
1588 rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_get_rate()
1589 PPLL); in rk3588_clk_get_rate()
1705 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
1706 priv->cru, PPLL); in rk3588_clk_set_rate()
1739 ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_set_rate()
1740 PPLL, rate); in rk3588_clk_set_rate()
1741 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
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| H A D | clk_rk3528.c | 75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
1359 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_get_rate()
1360 PPLL); in rk3528_clk_get_rate()
1481 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_set_rate()
1482 PPLL, rate); in rk3528_clk_set_rate()
1483 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], in rk3528_clk_set_rate()
1484 priv->cru, PPLL); in rk3528_clk_set_rate()
1957 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_init()
1958 PPLL, PPLL_HZ); in rk3528_clk_init()
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| H A D | clk_rk3576.c | 79 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
2063 priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], in rk3576_clk_get_rate()
2064 priv->cru, PPLL); in rk3576_clk_get_rate()
2095 rate = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], priv->cru, in rk3576_clk_get_rate()
2096 PPLL) * 2; in rk3576_clk_get_rate()
2227 priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], in rk3576_clk_set_rate()
2228 priv->cru, PPLL); in rk3576_clk_set_rate()
2261 ret = rockchip_pll_set_rate(&rk3576_pll_clks[PPLL], priv->cru, in rk3576_clk_set_rate()
2262 PPLL, rate); in rk3576_clk_set_rate()
2263 priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], in rk3576_clk_set_rate()
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| H A D | clk_rk1808.c | 90 [PPLL] = PLL(pll_rk3036, PLL_PPLL, RK1808_PMU_PLL_CON(0),
606 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[PPLL], in rk1808_mac_set_clk()
607 priv->cru, PPLL); in rk1808_mac_set_clk()
1005 ret = rockchip_pll_set_rate(&rk1808_pll_clks[PPLL], in rk1808_clk_set_rate()
1006 priv->cru, PPLL, rate); in rk1808_clk_set_rate()
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| H A D | clk_rk3568.c | 80 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
382 rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_get_rate()
383 priv->pmucru, PPLL); in rk3568_pmuclk_get_rate()
422 ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_set_rate()
423 priv->pmucru, PPLL, rate); in rk3568_pmuclk_set_rate()
424 priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_set_rate()
425 priv->pmucru, PPLL); in rk3568_pmuclk_set_rate()
494 ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_probe()
496 PPLL, PPLL_HZ); in rk3568_pmuclk_probe()
3286 priv->ppll_hz = rk3568_pmu_pll_get_rate(priv, PPLL); in rk3568_clk_init()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk1808.h | 25 PPLL, enumerator
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| H A D | cru_rk3528.h | 25 PPLL, enumerator
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| H A D | cru_rk3588.h | 31 PPLL, enumerator
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| H A D | cru_rk3568.h | 27 PPLL, enumerator
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| H A D | cru_rk3576.h | 31 PPLL, enumerator
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