66 	[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
1550 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_get_rate()
1551 						      priv->cru, PPLL);  in rk3588_clk_get_rate()
1588 		rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru,  in rk3588_clk_get_rate()
1589 					     PPLL);  in rk3588_clk_get_rate()
1705 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_set_rate()
1706 						      priv->cru, PPLL);  in rk3588_clk_set_rate()
1739 		ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,  in rk3588_clk_set_rate()
1740 					    PPLL, rate);  in rk3588_clk_set_rate()
1741 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_set_rate()
1742 						      priv->cru, PPLL);  in rk3588_clk_set_rate()
2085 		ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,  in rk3588_clk_init()
2086 					    PPLL, PPLL_HZ);  in rk3588_clk_init()
2087 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_init()
2088 						      priv->cru, PPLL);  in rk3588_clk_init()