clk/rockchip/clk_rk3576.c

79 	[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
2063 		priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],  in rk3576_clk_get_rate()
2064 						      priv->cru, PPLL);  in rk3576_clk_get_rate()
2095 		rate = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], priv->cru,  in rk3576_clk_get_rate()
2096 					     PPLL) * 2;  in rk3576_clk_get_rate()
2227 		priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],  in rk3576_clk_set_rate()
2228 						      priv->cru, PPLL);  in rk3576_clk_set_rate()
2261 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[PPLL], priv->cru,  in rk3576_clk_set_rate()
2262 					    PPLL, rate);  in rk3576_clk_set_rate()
2263 		priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],  in rk3576_clk_set_rate()
2264 						      priv->cru, PPLL) * 2;  in rk3576_clk_set_rate()