| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 114 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3328_PLL_CON(40),
135 old_rate = rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], in rk3328_armclk_set_clk()
136 priv->cru, NPLL); in rk3328_armclk_set_clk()
138 if (rockchip_pll_set_rate(&rk3328_pll_clks[NPLL], in rk3328_armclk_set_clk()
139 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
158 if (rockchip_pll_set_rate(&rk3328_pll_clks[NPLL], in rk3328_armclk_set_clk()
159 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
163 return rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], priv->cru, NPLL); in rk3328_armclk_set_clk()
809 rate = rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], in rk3328_clk_get_rate()
810 priv->cru, NPLL); in rk3328_clk_get_rate()
[all …]
|
| H A D | clk_rk1808.c | 88 [NPLL] = PLL(pll_rk3036, PLL_NPLL, RK1808_PLL_CON(32),
493 parent = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_vop_get_clk()
494 priv->cru, NPLL); in rk1808_vop_get_clk()
502 parent = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_vop_get_clk()
503 priv->cru, NPLL); in rk1808_vop_get_clk()
556 rockchip_pll_set_rate(&rk1808_pll_clks[NPLL], in rk1808_vop_set_clk()
557 priv->cru, NPLL, src_clk_div * hz); in rk1808_vop_set_clk()
574 rockchip_pll_set_rate(&rk1808_pll_clks[NPLL], in rk1808_vop_set_clk()
575 priv->cru, NPLL, in rk1808_vop_set_clk()
603 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_mac_set_clk()
[all …]
|
| H A D | clk_px30.c | 828 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); in px30_vop_get_clk()
871 npll_hz = px30_clk_get_pll_rate(priv, NPLL); in px30_vop_set_clk()
884 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); in px30_vop_set_clk()
1176 pll_rate = px30_clk_get_pll_rate(priv, NPLL); in px30_mac_set_clk()
1312 rate = px30_clk_get_pll_rate(priv, NPLL); in px30_clk_get_rate()
1397 ret = px30_clk_set_pll_rate(priv, NPLL, rate); in px30_clk_set_rate()
1920 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); in px30_clk_init()
1922 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); in px30_clk_init()
|
| H A D | clk_rk3368.c | 746 parent = rkclk_pll_get_rate(cru, NPLL); in rk3368_vop_get_clk()
777 rkclk_set_pll(cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_vop_set_clk()
784 rkclk_set_pll(cru, NPLL, &npll_config); in rk3368_vop_set_clk()
1309 rkclk_set_pll(priv->cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_clk_probe()
|
| H A D | clk_rk3588.c | 64 [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
1576 rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_get_rate()
1577 NPLL); in rk3588_clk_get_rate()
1723 ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_set_rate()
1724 NPLL, rate); in rk3588_clk_set_rate()
|
| H A D | clk_rk3568.c | 76 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
2542 rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru, in rk3568_clk_get_rate()
2543 NPLL); in rk3568_clk_get_rate()
2729 ret = rockchip_pll_set_rate(&rk3568_pll_clks[NPLL], priv->cru, in rk3568_clk_set_rate()
2730 NPLL, rate); in rk3568_clk_set_rate()
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 19 NPLL, enumerator
|
| H A D | cru_rk322x.h | 64 NPLL, enumerator
|
| H A D | cru_rk3328.h | 62 NPLL, enumerator
|
| H A D | cru_rk1808.h | 24 NPLL, enumerator
|
| H A D | cru_px30.h | 30 NPLL, enumerator
|
| H A D | cru_rk3588.h | 28 NPLL, enumerator
|
| H A D | cru_rk3568.h | 25 NPLL, enumerator
|