| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm.h | 19 #define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x070)
58 #define INFRA_AO_DBG_CON0 (INFRACFG_AO_BASE + 0x500)
59 #define INFRA_AO_DBG_CON1 (INFRACFG_AO_BASE + 0x504)
60 #define INFRA_AO_DBG_CON2 (INFRACFG_AO_BASE + 0x508)
61 #define INFRA_AO_DBG_CON3 (INFRACFG_AO_BASE + 0x50C)
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| H A D | mt_spm_hwreq.h | 198 #define INFRA_AO_OFFSET(offset) (INFRACFG_AO_BASE + offset)
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm.h | 18 #define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x070)
57 #define INFRA_AO_DBG_CON0 (INFRACFG_AO_BASE + 0x500)
58 #define INFRA_AO_DBG_CON1 (INFRACFG_AO_BASE + 0x504)
59 #define INFRA_AO_DBG_CON2 (INFRACFG_AO_BASE + 0x508)
60 #define INFRA_AO_DBG_CON3 (INFRACFG_AO_BASE + 0x50C)
66 #define MODULE_SW_CG_0_MASK (INFRACFG_AO_BASE + 0x060)
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| H A D | mt_spm_hwreq.h | 155 #define INFRA_AO_OFFSET(offset) (INFRACFG_AO_BASE + offset)
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| /rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/mt8189/ |
| H A D | mtcmos.h | 23 #define PERISYS_PROTECT_EN_STA_0 (INFRACFG_AO_BASE + 0x0C80)
24 #define PERISYS_PROTECT_EN_STA_0_SET (INFRACFG_AO_BASE + 0x0C84)
25 #define PERISYS_PROTECT_EN_STA_0_CLR (INFRACFG_AO_BASE + 0x0C88)
26 #define PERISYS_PROTECT_RDY_STA_0 (INFRACFG_AO_BASE + 0x0C8C)
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| /rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8186/ |
| H A D | rng_plat.h | 25 #define TRNG_PDN_SET (INFRACFG_AO_BASE + 0x0088)
26 #define TRNG_PDN_CLR (INFRACFG_AO_BASE + 0x008C)
27 #define TRNG_PDN_STATUS (INFRACFG_AO_BASE + 0x0094)
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| /rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8188/ |
| H A D | rng_plat.h | 42 #define TRNG_SWRST_SET_REG (INFRACFG_AO_BASE + 0x150)
43 #define TRNG_SWRST_CLR_REG (INFRACFG_AO_BASE + 0x154)
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| /rk3399_ARM-atf/plat/mediatek/drivers/thermal/mt8189/ |
| H A D | soc_temp_lvts.h | 11 #define THERM_MODULE_SW_CG_0_SET (INFRACFG_AO_BASE + 0x80)
12 #define THERM_MODULE_SW_CG_0_CLR (INFRACFG_AO_BASE + 0x84)
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/ |
| H A D | mtspmc_private.h | 118 #define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250)
119 #define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258)
120 #define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8)
121 #define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC)
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| /rk3399_ARM-atf/plat/mediatek/drivers/uart/ |
| H A D | uart.h | 17 #define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80)
18 #define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84)
19 #define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90)
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| /rk3399_ARM-atf/plat/mediatek/mt8186/include/ |
| H A D | platform_def.h | 26 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
42 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_extern.c | 11 #define INFRA_AO_RES_CTRL_MASK (INFRACFG_AO_BASE + 0xB8)
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| H A D | mt_spm_cond.c | 17 #define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
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| /rk3399_ARM-atf/plat/mediatek/mt8183/include/ |
| H A D | platform_def.h | 16 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) macro
40 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) macro
56 #define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0)
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| H A D | mcucfg.h | 268 INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250,
269 INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258,
270 INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8,
271 INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC
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| /rk3399_ARM-atf/plat/mediatek/mt8192/include/ |
| H A D | platform_def.h | 40 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8173/include/ |
| H A D | mt8173_def.h | 18 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8195/include/ |
| H A D | platform_def.h | 35 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8189/include/ |
| H A D | platform_def.h | 45 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8188/include/ |
| H A D | platform_def.h | 88 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/ |
| H A D | mtspmc_private.h | 34 #define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/ |
| H A D | mtspmc_private.h | 32 #define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/ |
| H A D | mtspmc_private.h | 34 #define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
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| /rk3399_ARM-atf/plat/mediatek/mt8196/include/ |
| H A D | platform_def.h | 131 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_cond.c | 19 #define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
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