1*3da2d29cSRaymond Sun /* 2*3da2d29cSRaymond Sun * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*3da2d29cSRaymond Sun * 4*3da2d29cSRaymond Sun * SPDX-License-Identifier: BSD-3-Clause 5*3da2d29cSRaymond Sun */ 6*3da2d29cSRaymond Sun 7*3da2d29cSRaymond Sun #ifndef MTK_SOC_TEMP_LVTS_H 8*3da2d29cSRaymond Sun #define MTK_SOC_TEMP_LVTS_H 9*3da2d29cSRaymond Sun 10*3da2d29cSRaymond Sun /* Definition or macro function */ 11*3da2d29cSRaymond Sun #define THERM_MODULE_SW_CG_0_SET (INFRACFG_AO_BASE + 0x80) 12*3da2d29cSRaymond Sun #define THERM_MODULE_SW_CG_0_CLR (INFRACFG_AO_BASE + 0x84) 13*3da2d29cSRaymond Sun #define THERM_BIT (10) 14*3da2d29cSRaymond Sun 15*3da2d29cSRaymond Sun #define THERMAL_REBOOT_TEMPERATURE (119000) 16*3da2d29cSRaymond Sun 17*3da2d29cSRaymond Sun #define DEFAULT_EFUSE_GOLDEN_TEMP (50) 18*3da2d29cSRaymond Sun #define DEFAULT_EFUSE_GOLDEN_TEMP_HT (170) 19*3da2d29cSRaymond Sun #define DEFAULT_EFUSE_COUNT (35000) 20*3da2d29cSRaymond Sun #define DEFAULT_EFUSE_COUNT_RC (2750) 21*3da2d29cSRaymond Sun 22*3da2d29cSRaymond Sun /* LVTS reset address */ 23*3da2d29cSRaymond Sun #define THERM_AP_RESET_SET_OFFSET 0xf50 24*3da2d29cSRaymond Sun #define THERM_AP_RESET_CLR_OFFSET 0xf54 25*3da2d29cSRaymond Sun #define THERM_AP_RESET_SET_BITNUM 23 26*3da2d29cSRaymond Sun #define THERM_AP_RESET_CLR_BITNUM 23 27*3da2d29cSRaymond Sun 28*3da2d29cSRaymond Sun #define THERM_MCU_RESET_SET_OFFSET 0xf20 29*3da2d29cSRaymond Sun #define THERM_MCU_RESET_CLR_OFFSET 0xf24 30*3da2d29cSRaymond Sun #define THERM_MCU_RESET_SET_BITNUM 12 31*3da2d29cSRaymond Sun #define THERM_MCU_RESET_CLR_BITNUM 12 32*3da2d29cSRaymond Sun 33*3da2d29cSRaymond Sun /* LVTS efuse address */ 34*3da2d29cSRaymond Sun #define NUM_EFUSE_ADDR 23 35*3da2d29cSRaymond Sun 36*3da2d29cSRaymond Sun /* LVTS v1 common code */ 37*3da2d29cSRaymond Sun #define SET_LVTS_MANUAL_RCK_V1 (DEVICE_WRITE | RG_TSV2F_CTRL_6 << 8 | 0x00) 38*3da2d29cSRaymond Sun #define SELECT_SENSOR_RCK_V1(id) (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | id) 39*3da2d29cSRaymond Sun #define KICK_OFF_RCK_COUNTING_V1 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x02) 40*3da2d29cSRaymond Sun #define SET_SENSOR_NO_RCK_V1 (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | 0x10) 41*3da2d29cSRaymond Sun #define SET_DEVICE_LOW_POWER_SINGLE_MODE_V1 (DEVICE_WRITE \ 42*3da2d29cSRaymond Sun | RG_TSFM_CTRL_3 << 8 | 0xF8) 43*3da2d29cSRaymond Sun 44*3da2d29cSRaymond Sun /* LVTS MT8189 */ 45*3da2d29cSRaymond Sun #define SET_DEVICE_SINGLE_MODE_8189 (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0x78) 46*3da2d29cSRaymond Sun #define SET_TS_DIS_8189 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF1) 47*3da2d29cSRaymond Sun #define SET_LVTS_MANUAL_RCK_OPERATION_8189 (DEVICE_WRITE \ 48*3da2d29cSRaymond Sun | RG_TSV2F_CTRL_6 << 8 | 0x00) 49*3da2d29cSRaymond Sun #define SET_TS_DIV_EN_8189 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF5) 50*3da2d29cSRaymond Sun #define SET_VCO_RST_8189 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xFD) 51*3da2d29cSRaymond Sun #define COF_A_T_SLP_GLD 219960 52*3da2d29cSRaymond Sun #define COF_A_COUNT_R_GLD 14437 53*3da2d29cSRaymond Sun #define COF_A_CONST_OFS 280000 54*3da2d29cSRaymond Sun #define COF_A_OFS (COF_A_T_SLP_GLD - COF_A_CONST_OFS) 55*3da2d29cSRaymond Sun 56*3da2d29cSRaymond Sun #endif /* MTK_SOC_TEMP_LVTS_H */ 57