1d8c718c5Sirving-ch-lin /* 2d8c718c5Sirving-ch-lin * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3d8c718c5Sirving-ch-lin * 4d8c718c5Sirving-ch-lin * SPDX-License-Identifier: BSD-3-Clause 5d8c718c5Sirving-ch-lin */ 6d8c718c5Sirving-ch-lin 7d8c718c5Sirving-ch-lin #ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ 8d8c718c5Sirving-ch-lin #define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ 9d8c718c5Sirving-ch-lin 10*68514bd9Sirving-ch-lin #include <lib/utils_def.h> 11d8c718c5Sirving-ch-lin #include <mtcmos_common.h> 12d8c718c5Sirving-ch-lin #include <platform_def.h> 13d8c718c5Sirving-ch-lin 14d8c718c5Sirving-ch-lin #define RTFF_SAVE BIT(24) 15d8c718c5Sirving-ch-lin #define RTFF_NRESTORE BIT(25) 16d8c718c5Sirving-ch-lin #define RTFF_CLK_DIS BIT(28) 17d8c718c5Sirving-ch-lin 18d8c718c5Sirving-ch-lin #define VLPCFG_REG_BASE (0x1C00C000) 19d8c718c5Sirving-ch-lin #define POWERON_CONFIG_EN (SPM_BASE + 0x0) 20d8c718c5Sirving-ch-lin #define UFS0_PWR_CON (SPM_BASE + 0x0E10) 21d8c718c5Sirving-ch-lin #define UFS0_PHY_PWR_CON (SPM_BASE + 0x0E14) 22d8c718c5Sirving-ch-lin 23d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_EN_STA_0 (INFRACFG_AO_BASE + 0x0C80) 24d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_EN_STA_0_SET (INFRACFG_AO_BASE + 0x0C84) 25d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_EN_STA_0_CLR (INFRACFG_AO_BASE + 0x0C88) 26d8c718c5Sirving-ch-lin #define PERISYS_PROTECT_RDY_STA_0 (INFRACFG_AO_BASE + 0x0C8C) 27d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN (VLPCFG_REG_BASE + 0x0210) 28d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN_SET (VLPCFG_REG_BASE + 0x0214) 29d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN_CLR (VLPCFG_REG_BASE + 0x0218) 30d8c718c5Sirving-ch-lin #define VLP_TOPAXI_PROTECTEN_STA1 (VLPCFG_REG_BASE + 0x0220) 31d8c718c5Sirving-ch-lin 32d8c718c5Sirving-ch-lin #define UFS0_PROT_STEP1_0_MASK BIT(5) 33d8c718c5Sirving-ch-lin #define UFS0_PROT_STEP2_0_MASK BIT(4) 34d8c718c5Sirving-ch-lin #define UFS0_PROT_STEP3_0_MASK BIT(6) 35d8c718c5Sirving-ch-lin 36d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_set_table[] = { 37d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_SET, VLP_TOPAXI_PROTECTEN_STA1, UFS0_PROT_STEP1_0_MASK}, 38d8c718c5Sirving-ch-lin {PERISYS_PROTECT_EN_STA_0_SET, PERISYS_PROTECT_RDY_STA_0, UFS0_PROT_STEP2_0_MASK}, 39d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_SET, VLP_TOPAXI_PROTECTEN_STA1, UFS0_PROT_STEP3_0_MASK}, 40d8c718c5Sirving-ch-lin }; 41d8c718c5Sirving-ch-lin 42d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_bus_prot_clr_table[] = { 43d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_CLR, 0x0, UFS0_PROT_STEP3_0_MASK}, 44d8c718c5Sirving-ch-lin {PERISYS_PROTECT_EN_STA_0_CLR, 0x0, UFS0_PROT_STEP2_0_MASK}, 45d8c718c5Sirving-ch-lin {VLP_TOPAXI_PROTECTEN_CLR, 0x0, UFS0_PROT_STEP1_0_MASK}, 46d8c718c5Sirving-ch-lin }; 47d8c718c5Sirving-ch-lin 48d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_set_table[] = {}; 49d8c718c5Sirving-ch-lin static const struct bus_protect ufs0_phy_bus_prot_clr_table[] = {}; 50d8c718c5Sirving-ch-lin 51d8c718c5Sirving-ch-lin #endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8189_MTCMOS_H_ */ 52