1*7ac6a76cSjason-ch chen /* 2*7ac6a76cSjason-ch chen * Copyright (c) since 2022, ARM Limited and Contributors. All rights reserved. 3*7ac6a76cSjason-ch chen * 4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 5*7ac6a76cSjason-ch chen */ 6*7ac6a76cSjason-ch chen 7*7ac6a76cSjason-ch chen #include <common/debug.h> 8*7ac6a76cSjason-ch chen #include <lib/mmio.h> 9*7ac6a76cSjason-ch chen #include <platform_def.h> 10*7ac6a76cSjason-ch chen 11*7ac6a76cSjason-ch chen #define INFRA_AO_RES_CTRL_MASK (INFRACFG_AO_BASE + 0xB8) 12*7ac6a76cSjason-ch chen #define INFRA_AO_RES_CTRL_MASK_EMI_IDLE BIT(18) 13*7ac6a76cSjason-ch chen #define INFRA_AO_RES_CTRL_MASK_MPU_IDLE BIT(15) 14*7ac6a76cSjason-ch chen spm_extern_initialize(void)15*7ac6a76cSjason-ch chenvoid spm_extern_initialize(void) 16*7ac6a76cSjason-ch chen { 17*7ac6a76cSjason-ch chen unsigned int val; 18*7ac6a76cSjason-ch chen 19*7ac6a76cSjason-ch chen val = mmio_read_32(INFRA_AO_RES_CTRL_MASK); 20*7ac6a76cSjason-ch chen 21*7ac6a76cSjason-ch chen val |= (INFRA_AO_RES_CTRL_MASK_EMI_IDLE | INFRA_AO_RES_CTRL_MASK_MPU_IDLE); 22*7ac6a76cSjason-ch chen mmio_write_32(INFRA_AO_RES_CTRL_MASK, val); 23*7ac6a76cSjason-ch chen } 24