1*3374752fSBo-Chen Chen /* 2*3374752fSBo-Chen Chen * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*3374752fSBo-Chen Chen * 4*3374752fSBo-Chen Chen * SPDX-License-Identifier: BSD-3-Clause 5*3374752fSBo-Chen Chen */ 6*3374752fSBo-Chen Chen 7*3374752fSBo-Chen Chen #ifndef UART_H 8*3374752fSBo-Chen Chen #define UART_H 9*3374752fSBo-Chen Chen 10*3374752fSBo-Chen Chen #include <platform_def.h> 11*3374752fSBo-Chen Chen 12*3374752fSBo-Chen Chen /* UART HW information */ 13*3374752fSBo-Chen Chen #define HW_SUPPORT_UART_PORTS 2 14*3374752fSBo-Chen Chen #define DRV_SUPPORT_UART_PORTS 2 15*3374752fSBo-Chen Chen 16*3374752fSBo-Chen Chen /* console UART clock cg */ 17*3374752fSBo-Chen Chen #define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80) 18*3374752fSBo-Chen Chen #define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84) 19*3374752fSBo-Chen Chen #define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90) 20*3374752fSBo-Chen Chen #define UART0_CLOCK_GATE_BIT (1U<<22) 21*3374752fSBo-Chen Chen #define UART1_CLOCK_GATE_BIT (1U<<23) 22*3374752fSBo-Chen Chen 23*3374752fSBo-Chen Chen /* UART registers */ 24*3374752fSBo-Chen Chen #define UART_RBR(_baseaddr) (_baseaddr + 0x0) 25*3374752fSBo-Chen Chen #define UART_THR(_baseaddr) (_baseaddr + 0x0) 26*3374752fSBo-Chen Chen #define UART_IER(_baseaddr) (_baseaddr + 0x4) 27*3374752fSBo-Chen Chen #define UART_IIR(_baseaddr) (_baseaddr + 0x8) 28*3374752fSBo-Chen Chen #define UART_FCR(_baseaddr) (_baseaddr + 0x8) 29*3374752fSBo-Chen Chen #define UART_LCR(_baseaddr) (_baseaddr + 0xc) 30*3374752fSBo-Chen Chen #define UART_MCR(_baseaddr) (_baseaddr + 0x10) 31*3374752fSBo-Chen Chen #define UART_LSR(_baseaddr) (_baseaddr + 0x14) 32*3374752fSBo-Chen Chen #define UART_MSR(_baseaddr) (_baseaddr + 0x18) 33*3374752fSBo-Chen Chen #define UART_SCR(_baseaddr) (_baseaddr + 0x1c) 34*3374752fSBo-Chen Chen #define UART_DLL(_baseaddr) (_baseaddr + 0x0) 35*3374752fSBo-Chen Chen #define UART_DLH(_baseaddr) (_baseaddr + 0x4) 36*3374752fSBo-Chen Chen #define UART_EFR(_baseaddr) (_baseaddr + 0x8) 37*3374752fSBo-Chen Chen #define UART_XON1(_baseaddr) (_baseaddr + 0x10) 38*3374752fSBo-Chen Chen #define UART_XON2(_baseaddr) (_baseaddr + 0x14) 39*3374752fSBo-Chen Chen #define UART_XOFF1(_baseaddr) (_baseaddr + 0x18) 40*3374752fSBo-Chen Chen #define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c) 41*3374752fSBo-Chen Chen #define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20) 42*3374752fSBo-Chen Chen #define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24) 43*3374752fSBo-Chen Chen #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28) 44*3374752fSBo-Chen Chen #define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c) 45*3374752fSBo-Chen Chen #define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30) 46*3374752fSBo-Chen Chen #define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34) 47*3374752fSBo-Chen Chen #define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38) 48*3374752fSBo-Chen Chen #define UART_GUARD(_baseaddr) (_baseaddr + 0x3c) 49*3374752fSBo-Chen Chen #define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40) 50*3374752fSBo-Chen Chen #define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44) 51*3374752fSBo-Chen Chen #define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48) 52*3374752fSBo-Chen Chen #define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c) 53*3374752fSBo-Chen Chen #define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50) 54*3374752fSBo-Chen Chen #define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54) 55*3374752fSBo-Chen Chen #define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58) 56*3374752fSBo-Chen Chen #define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C) 57*3374752fSBo-Chen Chen #define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0) 58*3374752fSBo-Chen Chen #define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4) 59*3374752fSBo-Chen Chen #define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8) 60*3374752fSBo-Chen Chen #define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC) 61*3374752fSBo-Chen Chen #define UART_LCR_DLAB 0x0080 62*3374752fSBo-Chen Chen #define UART_LCR_MODE_B 0x00bf 63*3374752fSBo-Chen Chen 64*3374752fSBo-Chen Chen enum uart_port_ID { 65*3374752fSBo-Chen Chen UART_PORT0 = 0, 66*3374752fSBo-Chen Chen UART_PORT1 67*3374752fSBo-Chen Chen }; 68*3374752fSBo-Chen Chen 69*3374752fSBo-Chen Chen struct mt_uart_register { 70*3374752fSBo-Chen Chen uint32_t dll; 71*3374752fSBo-Chen Chen uint32_t dlh; 72*3374752fSBo-Chen Chen uint32_t ier; 73*3374752fSBo-Chen Chen uint32_t lcr; 74*3374752fSBo-Chen Chen uint32_t mcr; 75*3374752fSBo-Chen Chen uint32_t fcr; 76*3374752fSBo-Chen Chen uint32_t lsr; 77*3374752fSBo-Chen Chen uint32_t scr; 78*3374752fSBo-Chen Chen uint32_t efr; 79*3374752fSBo-Chen Chen uint32_t highspeed; 80*3374752fSBo-Chen Chen uint32_t sample_count; 81*3374752fSBo-Chen Chen uint32_t sample_point; 82*3374752fSBo-Chen Chen uint32_t fracdiv_l; 83*3374752fSBo-Chen Chen uint32_t fracdiv_m; 84*3374752fSBo-Chen Chen uint32_t escape_en; 85*3374752fSBo-Chen Chen uint32_t guard; 86*3374752fSBo-Chen Chen uint32_t rx_sel; 87*3374752fSBo-Chen Chen }; 88*3374752fSBo-Chen Chen 89*3374752fSBo-Chen Chen struct mt_uart { 90*3374752fSBo-Chen Chen unsigned long base; 91*3374752fSBo-Chen Chen struct mt_uart_register registers; 92*3374752fSBo-Chen Chen }; 93*3374752fSBo-Chen Chen 94*3374752fSBo-Chen Chen /* external API */ 95*3374752fSBo-Chen Chen void mt_uart_save(void); 96*3374752fSBo-Chen Chen void mt_uart_restore(void); 97*3374752fSBo-Chen Chen void mt_console_uart_cg(int on); 98*3374752fSBo-Chen Chen uint32_t mt_console_uart_cg_status(void); 99*3374752fSBo-Chen Chen 100*3374752fSBo-Chen Chen #endif /* __UART_H__ */ 101