| #
d684e7fb |
| 29-Oct-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(mt8186): add common and MT8186 TRNG driver" into integration
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| #
8c1740e2 |
| 19-Sep-2024 |
Suyuan Su <suyuan.su@mediatek.com> |
feat(mt8186): add common and MT8186 TRNG driver
Introduce a common RNG driver along with the specific driver for MT8186
platform.
Change-Id: I9f4437b6a4b3e8564a035ff5abb681bcfe85bd1e
Signed-off-by:
feat(mt8186): add common and MT8186 TRNG driver
Introduce a common RNG driver along with the specific driver for MT8186
platform.
Change-Id: I9f4437b6a4b3e8564a035ff5abb681bcfe85bd1e
Signed-off-by: Suyuan Su <suyuan.su@mediatek.com>
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
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| #
f3ea17c3 |
| 02-Jul-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(mediatek): configure DEV_IRQ as G1S interrupt" into integration
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| #
240a1ecd |
| 17-Jun-2024 |
Gavin Liu <gavin.liu@mediatek.com> |
feat(mediatek): configure DEV_IRQ as G1S interrupt
In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK
feat(mediatek): configure DEV_IRQ as G1S interrupt
In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846
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| #
bbdf2591 |
| 08-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Idde51a13,Ife8f1e84 into integration
* changes:
feat(mediatek): add smcc call for MSDC
refactor(mediatek): refactor plat_sip_calls.h for mt8192/mt8195/mt8186
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| #
4dbe24cf |
| 22-Jun-2022 |
Bo-Chen Chen <rex-bc.chen@mediatek.com> |
feat(mediatek): add smcc call for MSDC
Some registers of MSDC need to be set in ATF, so we add MSDC drivers.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idde51a136ad08dbaece0b
feat(mediatek): add smcc call for MSDC
Some registers of MSDC need to be set in ATF, so we add MSDC drivers.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idde51a136ad08dbaece0bdaa804b934fca7046b6
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| #
a2025603 |
| 19-Jul-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(mt8186): move SSPM base register definition to platform_def.h" into integration
|
| #
2a2b51d8 |
| 08-Jul-2022 |
Yidi Lin <yidilin@chromium.org> |
fix(mt8186): move SSPM base register definition to platform_def.h
- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.
Sig
fix(mt8186): move SSPM base register definition to platform_def.h
- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ibb0291ce7b7426068392e90bd70f29d1a90d5297
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| #
1f4adc3a |
| 13-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I52b241b2,I25b4b97c into integration
* changes:
feat(mt8186): add Vcore DVFS driver
feat(mt8186): add SPM suspend driver
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| #
635e6b10 |
| 16-Nov-2021 |
jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> |
feat(mt8186): add Vcore DVFS driver
Add Vcore DVFS to SPM driver.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I52b241b2cdb792be74390cbaa09a
feat(mt8186): add Vcore DVFS driver
Add Vcore DVFS to SPM driver.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I52b241b2cdb792be74390cbaa09a728ddbe6593a
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| #
7ac6a76c |
| 16-Nov-2021 |
jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> |
feat(mt8186): add SPM suspend driver
Add SPM suspend driver for suspend/resume features.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I25b4b
feat(mt8186): add SPM suspend driver
Add SPM suspend driver for suspend/resume features.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I25b4b97cd3138a7b347385539e47ccfa884d64fc
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| #
ed780b0b |
| 22-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I41001484,Ic734696a,I84741535,I85aaaf3a,Ibd5423b7, ... into integration
* changes:
feat(plat/mediatek/mt8186): add reboot function for PSCI
feat(plat/mdeiatek/mt8186): add power-of
Merge changes I41001484,Ic734696a,I84741535,I85aaaf3a,Ibd5423b7, ... into integration
* changes:
feat(plat/mediatek/mt8186): add reboot function for PSCI
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
feat(plat/mediatek/mt8186): apply erratas for MT8186
feat(plat/mediatek/mt8186): add MCDI drivers
feat(plat/mediatek/mt8186): add CPU hotplug
feat(plat/mediatek/mt8186): add RTC drivers
fix(plat/mediatek/mt8186): extend MMU region size
feat(plat/mediatek/mt8186): add DCM driver
feat(plat/mediatek/mt8186): add pinctrl support
feat(plat/mediatek/mt8186): add sys_cirq support
feat(plat/mediatek/mt8186): initialize GIC
feat(plat/mediatek/mt8186): add SiP service
feat(plat/mediatek/mt8186): add pwrap and pmic driver
feat(plat/mediatek/mt8186): initialize delay_timer
feat(plat/mediatek/mt8186): initialize systimer
feat(plat/mediatek/mt8186): add EMI MPU basic driver
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|
| #
1da57e54 |
| 08-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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|
| #
0fe7ae9c |
| 09-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I520c51338578bd68756cd02603ce6783f93daf51
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|
| #
af5a0c40 |
| 15-Oct-2021 |
Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f
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|
| #
109b91e3 |
| 12-Oct-2021 |
Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787
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|
| #
206f125c |
| 11-Oct-2021 |
Christine Zhu <christine.zhu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d02
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d029983c7ce48fa116fafa7fa78c65349308014
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|
| #
5bc88ec6 |
| 06-Oct-2021 |
James Lo <james.lo@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jame
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2
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|
| #
1b17e34c |
| 03-Oct-2021 |
Penny Jan <penny.jan@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and w
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and will add more settings for
EMI MPU in next patch.
TEST=build pass
BUG=b:202871018
Signed-off-by: Penny Jan <penny.jan@mediatek.corp-partner.google.com>
Change-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e
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|
| #
e018bf71 |
| 01-Dec-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(mt8186): initialize platform for MediaTek MT8186" into integration
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| #
27132f13 |
| 28-Sep-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
TEST=bu
feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
show more ...
|