| #
f3ea17c3 |
| 02-Jul-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(mediatek): configure DEV_IRQ as G1S interrupt" into integration
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| #
240a1ecd |
| 17-Jun-2024 |
Gavin Liu <gavin.liu@mediatek.com> |
feat(mediatek): configure DEV_IRQ as G1S interrupt
In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK
feat(mediatek): configure DEV_IRQ as G1S interrupt
In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846
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| #
4a2ff22f |
| 25-Oct-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(mt8195): increase TZRAM" into integration
|
| #
4f79b672 |
| 22-May-2023 |
Yi Chou <yich@google.com> |
feat(mt8195): increase TZRAM
We need 4k more memory.
Change-Id: I760e949c2f80a79e111060b24855c0a6a5bfdfaa
Signed-off-by: Yi Chou <yich@google.com>
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| #
04f28f89 |
| 05-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mt8188" into integration
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move
Merge changes from topic "mt8188" into integration
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move pmic.[c|h] to common folder
refator(mediatek): move common definitions of pmic wrap to common folder
feat(mt8188): add IOMMU enable control in SiP service
feat(mt8188): add display port control in SiP service
fix(mediatek): use uppercase for definition
feat(mediatek): move dp drivers to common folder
feat(mediatek): move mtk_cirq.c drivers to cirq folder
feat(mt8188): initialize GIC
feat(mt8188): initialize systimer
feat(mt8188): initialize platform for MediaTek MT8188
refator(mediatek): remove unused files
refator(mediatek): move drivers folder in common to plat/mediatek
feat(mediatek): support coreboot BL31 loading
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| #
810d5681 |
| 12-Jul-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
fix(mediatek): use uppercase for definition
Use uppercase for definition.
s/eDP_SEC_BASE/EDP_SEC_BASE/.
s/eDP_SEC_SIZE/EDP_SEC_SIZE/.
TEST=build pass for mt8195
BUG=b:233720142
Signed-off-by: Bo-C
fix(mediatek): use uppercase for definition
Use uppercase for definition.
s/eDP_SEC_BASE/EDP_SEC_BASE/.
s/eDP_SEC_SIZE/EDP_SEC_SIZE/.
TEST=build pass for mt8195
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I390055500a6347b67fefde36a7f103438ba2d5ff
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| #
2141a685 |
| 01-Dec-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I0c1f7d6c,I3bec0b58,If24cf213 into integration
* changes:
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop S
Merge changes I0c1f7d6c,I3bec0b58,If24cf213 into integration
* changes:
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
feat(plat/mediatek/apu): add mt8195 APU iommap regions
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| #
339e4924 |
| 01-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21
feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21318813babfc2c11f38891521c7106b58c
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| #
1b1123c5 |
| 06-Oct-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(plat/mdeiatek/mt8195): add DFD control in SiP service" into integration
|
| #
3b994a75 |
| 10-Aug-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those
feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
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| #
d2726117 |
| 15-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Iedc19d8f,Ic5fc78c9 into integration
* changes:
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
feat(plat/mediatek/mt8195): add vcore-dvfs support
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| #
75edd34a |
| 19-Aug-2021 |
Penny Jan <penny.jan@mediatek.com> |
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and
feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.
Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
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| #
d562130e |
| 09-Jul-2021 |
Dawei Chien <dawei.chien@mediatek.com> |
feat(plat/mediatek/mt8195): add vcore-dvfs support
Add DVFSRC init flow.
Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
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| #
7fa35d06 |
| 02-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ib8502f9b,I388fd231,I7bd37912,I3a186ed7 into integration
* changes:
feat(plat/mediatek/mt8195): add SPM suspend driver
feat(plat/mediatek/mt8195): support MCUSYS off when system su
Merge changes Ib8502f9b,I388fd231,I7bd37912,I3a186ed7 into integration
* changes:
feat(plat/mediatek/mt8195): add SPM suspend driver
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
feat(plat/mediatek/mt8195): add support for PTP3
fix(plat/mediatek/mt8195): extend MMU region size
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| #
d336e093 |
| 28-Jun-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.
feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
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| #
9ff8b8ca |
| 18-Jun-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
fix(plat/mediatek/mt8195): extend MMU region size
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8195): extend MMU region size
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8195 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
Change-Id: I3a186ed71d0d963b59ae55e27a6d27a01fe4f638
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| #
fb88c71d |
| 01-Jun-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/mdeiatek/mt8195): add display port control in SiP service" into integration
|
| #
7eb42237 |
| 12-Apr-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.c
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
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| #
a92b0256 |
| 26-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I20c73f6e,I9962263c,I177796e3,I6ff6875c,I21fe9d85, ... into integration
* changes:
mediatek: mt8195: add rtc power off sequence
mediatek: mt8195: add power-off support
mediatek:
Merge changes I20c73f6e,I9962263c,I177796e3,I6ff6875c,I21fe9d85, ... into integration
* changes:
mediatek: mt8195: add rtc power off sequence
mediatek: mt8195: add power-off support
mediatek: mt8195: Add reboot function for PSCI
mediatek: mt8195: Add gpio driver
mediatek: mt8195: Add SiP service
mediatek: mt8195: Add CPU hotplug and MCDI support
mediatek: mt8195: Add MCDI drivers
mediatek: mt8195: Add SPMC driver
mediatek: mt8195: Initialize delay_timer
mediatek: mt8195: initialize systimer
mediatek: mt8192: move timer driver to common folder
mediatek: mt8195: add sys_cirq support
mediatek: mt8195: initialize GIC
Initialize platform for MediaTek MT8195
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| #
0909819a |
| 08-Apr-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
mediatek: mt8195: add power-off support
mt8195 also uses PMIC mt6359p. The only difference is the
pwrap register definition.
Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0
Signed-off-by: Yidi
mediatek: mt8195: add power-off support
mt8195 also uses PMIC mt6359p. The only difference is the
pwrap register definition.
Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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| #
aebd4dc8 |
| 31-Mar-2021 |
mtk20895 <zhiqiang.ma@mediatek.com> |
mediatek: mt8195: Add gpio driver
Add gpio driver.
Signed-off-by: mtk20895 <zhiqiang.ma@mediatek.com>
Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
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| #
acc85548 |
| 15-Jun-2020 |
James Liao <jamesjj.liao@mediatek.com> |
mediatek: mt8195: Add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I6a6f9bf5d1d8bda1ee603d8bf3
mediatek: mt8195: Add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I6a6f9bf5d1d8bda1ee603d8bf3fc206437de7ad8
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| #
0d82eff6 |
| 16-Jun-2020 |
James Liao <jamesjj.liao@mediatek.com> |
mediatek: mt8195: Add SPMC driver
Add SPMC driver for CPU power on/off.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: If47d7f3f3b9965f3c0402ea6cdb917ad1d16bb32
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| #
e5490f95 |
| 25-Mar-2021 |
gtk_pangao <gtk_pangao@mediatek.com> |
mediatek: mt8195: add sys_cirq support
MT8192 cirq driver can be shared with MT8195. Move cirq driver to common
common folder.
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
Change-Id: Iba5cdc
mediatek: mt8195: add sys_cirq support
MT8192 cirq driver can be shared with MT8195. Move cirq driver to common
common folder.
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
Change-Id: Iba5cdcfd2116f0bd07e0497250f2da45613e3a4f
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| #
c63f1451 |
| 24-Mar-2021 |
christine.zhu <christine.zhu@mediatek.corp-partner.google.com> |
mediatek: mt8195: initialize GIC
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.
mediatek: mt8195: initialize GIC
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
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|