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Searched refs:BL2_BASE (Results 1 – 25 of 59) sorted by relevance

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/rk3399_ARM-atf/plat/brcm/board/stingray/include/
H A Dplatform_def.h112 #define BL2_BASE QSPI_BASE_ADDR macro
113 #define BL2_LIMIT (BL2_BASE + 0x40000)
118 #define BL2_BASE NAND_BASE_ADDR macro
119 #define BL2_LIMIT (BL2_BASE + 0x40000)
124 #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) macro
/rk3399_ARM-atf/tools/nxp/create_pbl/
H A Dpbl_ch2.mk26 …BL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
47 …L} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
H A Dpbl_ch3.mk34 …BL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
63 …L} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
/rk3399_ARM-atf/include/plat/arm/css/common/
H A Dcss_def.h188 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
189 #define SCP_BL2_LIMIT BL2_BASE
191 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
192 #define SCP_BL2U_LIMIT BL2_BASE
/rk3399_ARM-atf/plat/qti/kodiak/rb3gen2/inc/
H A Dplatform_def.h15 #define BL2_BASE 0x1c00e000 macro
17 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
/rk3399_ARM-atf/plat/renesas/common/include/
H A Dplatform_def.h115 #define BL2_BASE U(0xE6304000) macro
118 #define BL2_BASE U(0xE6344000) macro
121 #define BL2_BASE U(0xE6304000) macro
124 #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/rk3399_ARM-atf/bl2/
H A Dbl2.ld.S15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
21 . = BL2_BASE;
H A Dbl2_el3.ld.S19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
45 . = BL2_BASE;
/rk3399_ARM-atf/include/drivers/arm/css/
H A Dcss_scp.h45 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
46 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
/rk3399_ARM-atf/plat/hisilicon/poplar/include/
H A Dpoplar_layout.h125 #define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET) macro
126 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
/rk3399_ARM-atf/include/plat/nuvoton/common/
H A Dnpcm845x_arm_def.h443 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
450 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
470 #define BL31_NOBITS_BASE BL2_BASE
490 #define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */
495 #define BL31_PROGBITS_LIMIT BL2_BASE
502 #define BL31_LIMIT BL2_BASE
520 #define BL2U_BASE BL2_BASE
/rk3399_ARM-atf/plat/socionext/uniphier/include/
H A Dplatform_def.h53 #define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) macro
54 #define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dplatform_def.h61 #define BL2_BASE (0x1AC00000) macro
62 #define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
/rk3399_ARM-atf/bl1/tbbr/
H A Dtbbr_img_desc.c17 .image_info.image_base = BL2_BASE,
18 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,
/rk3399_ARM-atf/plat/nxp/common/plat_make_helper/
H A Dsoc_common_def.mk50 ifneq (${BL2_BASE},)
51 $(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
/rk3399_ARM-atf/include/plat/common/
H A Dcommon_def.h109 .image_info.image_base = BL2_BASE, \
110 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\
113 .ep_info.pc = BL2_BASE, \
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl1_plat_setup.c56 bl2_tzram_layout.total_base = BL2_BASE; in bl1_plat_handle_post_image_load()
57 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; in bl1_plat_handle_post_image_load()
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/
H A Dsoc.def64 BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
66 # BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD)
68 # overalp with BL2_BASE
/rk3399_ARM-atf/include/plat/arm/common/
H A Darm_def.h602 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
611 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
630 #define BL31_NOBITS_BASE BL2_BASE
648 #define BL31_PROGBITS_LIMIT BL2_BASE
655 #define BL31_LIMIT BL2_BASE
692 # define BL32_PROGBITS_LIMIT BL2_BASE
778 #define BL2U_BASE BL2_BASE
/rk3399_ARM-atf/drivers/arm/css/scp/
H A Dcss_bom_bootloader.c56 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
57 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/
H A Dsoc.def61 # BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
62 BL2_BASE := 0x1800a000
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c95 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c100 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/plat/socionext/synquacer/include/
H A Dplatform_def.h64 #define BL2_BASE 0x04000000 macro
66 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/ls1088ardb/
H A Dplat_def.h44 #define BL2_NOLOAD_LIMIT BL2_BASE

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