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833e3c40 |
| 02-Oct-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix: remove unused cpu_data related macros" into integration
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| #
2c730eea |
| 12-Sep-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix: remove unused cpu_data related macros
There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.
PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets to mismatch when t
fix: remove unused cpu_data related macros
There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.
PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets to mismatch when the linker garbage collects it. It is also removed.
CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in rcar_lock_get() and related macros which are never called since all calls of these macros lack an argument.
Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| #
4d877b35 |
| 14-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(rcar3-drivers): check loaded NS image area" into integration
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| #
ae4860b0 |
| 16-Mar-2023 |
Tobias Rist <tobias.rist@joynext.com> |
fix(rcar3-drivers): check loaded NS image area
Check if next NS image invades a previous loaded image. Correct non secure image area to avoid loading a NS image to secure
Move GZ compressed payload
fix(rcar3-drivers): check loaded NS image area
Check if next NS image invades a previous loaded image. Correct non secure image area to avoid loading a NS image to secure
Move GZ compressed payload at 32 * compressed payload size offset, so it is loaded in non-secure area and can be decompressed into non-secure area too. It is unlikely that the up to 2 MiB compressed BL33 blob would decompress to payload larger than 64 MiB .
Signed-off-by: Tobias Rist <tobias.rist@joynext.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Fix for compressed BL33 Change-Id: I52fd556aab50687e4791e5dbc45d425f802c8757
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| #
33b0c792 |
| 31-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I25047322,Id476f815 into integration
* changes: fix(plat/rcar3): change stack size of BL31 fix(plat/rcar3): fix SYSTEM_OFF processing for R-Car D3
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| #
d544dfcc |
| 01-Dec-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
fix(plat/rcar3): change stack size of BL31
Increase the stack size to avoid stack overflow when the LOG_LEVEL compile option is set high.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.co
fix(plat/rcar3): change stack size of BL31
Increase the stack size to avoid stack overflow when the LOG_LEVEL compile option is set high.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I25047322763bff148dba13848a3a40f4c7cf90b7
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| #
a6db44ad |
| 05-Oct-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration
* changes: feat(plat/rcar3): keep RWDT enabled feat(drivers/rcar3): add extra offset if booting B-side fea
Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration
* changes: feat(plat/rcar3): keep RWDT enabled feat(drivers/rcar3): add extra offset if booting B-side feat(plat/rcar3): modify LifeC register setting for R-Car D3 feat(plat/rcar3): modify SWDT counter setting for R-Car D3 feat(plat/rcar3): update DDR setting for R-Car D3 feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3 feat(plat/rcar3): add process of SSCG setting for R-Car D3 feat(plat/rcar3): add process to back up X6 and X7 register's value feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up feat(plat/rcar3): change the memory map for OP-TEE feat(plat/rcar3): use PRR cut to determine DRAM size on M3 feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537 fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3 fix(plat/rcar3): fix eMMC boot support for R-Car D3 fix(plat/rcar3): fix version judgment for R-Car D3 fix(plat/rcar3): fix source file to make about GICv2 fix(drivers/rcar3): console: fix a return value of console_rcar_init
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| #
a4d821a5 |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): change the memory map for OP-TEE
The memory area size of OP-TEE was changed from 1MB to 2MB because the size of OP-TEE has increased.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki
feat(plat/rcar3): change the memory map for OP-TEE
The memory area size of OP-TEE was changed from 1MB to 2MB because the size of OP-TEE has increased.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ic8a165c83a3a9ef2829f68d5fabeed9ccb6da95e
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| #
c87f2c1d |
| 13-Aug-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes: feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked feat(plat/rcar3): add a DRAM siz
Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes: feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked feat(plat/rcar3): add a DRAM size setting for M3N feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0 feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB feat(drivers/rcar3): ddr: add function to judge a DDR rank fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N fix(drivers/rcar3): i2c_dvfs: fix I2C operation fix(drivers/rcar3): fix CPG registers redefinition fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0 refactor(plat/rcar3): factor out DT memory node generation feat(plat/rcar3): add optional support for gzip-compressed BL33
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| #
ddf2ca03 |
| 13-Feb-2021 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
feat(plat/rcar3): add optional support for gzip-compressed BL33
The BL33 size on this platform is limited to 1 MiB, add optional support for decompressing and starting gzip-compressed BL33, which ma
feat(plat/rcar3): add optional support for gzip-compressed BL33
The BL33 size on this platform is limited to 1 MiB, add optional support for decompressing and starting gzip-compressed BL33, which may help with this size limitation. This functionality is disabled by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it.
The BL33 at 0x50000000 should then be gzip compressed, however if the BL33 does not have a valid gzip header, it is copied to the correct location and started as-is, this is a fallback for legacy systems and systems which update to gzip-compressed BL33.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa
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| #
fc037ffc |
| 14-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration
* changes: drivers: renesas: Move plat common sources plat: renesas: Move headers and assembly files to comm
Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration
* changes: drivers: renesas: Move plat common sources plat: renesas: Move headers and assembly files to common folder plat: renesas: rcar: include: Code cleanup plat: renesas:rcar: Fix checkpatch warnings plat: renesas: rcar: Fix checkpatch warnings plat: renesas:rcar: Code cleanup plat: renesas: rcar: Fix coding style
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011a4c2f |
| 16-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
plat: renesas: Move headers and assembly files to common folder
Create a common directory and move the header and assembly files so that the common code can be used by both Renesas R-Car Gen3 and RZ
plat: renesas: Move headers and assembly files to common folder
Create a common directory and move the header and assembly files so that the common code can be used by both Renesas R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: Ia9a563a1c3c9f8c6f0d3cb82622deb2e155d7f6c
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