1*ceae3743SBiwen Li# Copyright 2020-2022 NXP 29398841eSJiafei Pan# 39398841eSJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 49398841eSJiafei Pan# 59398841eSJiafei Pan 69398841eSJiafei Pan# Adding SoC specific defines 79398841eSJiafei Pan 89398841eSJiafei Panifneq (${CACHE_LINE},) 99398841eSJiafei Pan$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE})) 109398841eSJiafei Pan$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE))))) 119398841eSJiafei Pan$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE))) 129398841eSJiafei Panendif 139398841eSJiafei Pan 14*ceae3743SBiwen Liifneq (${INTERCONNECT},) 159398841eSJiafei Pan$(eval $(call add_define,NXP_HAS_${INTERCONNECT})) 16*ceae3743SBiwen Liifeq (${INTERCONNECT}, CCI400) 179398841eSJiafei PanICNNCT_ID := 0x420 189398841eSJiafei Pan$(eval $(call add_define,ICNNCT_ID)) 199398841eSJiafei Panendif 209398841eSJiafei Panendif 219398841eSJiafei Pan 229398841eSJiafei Panifneq (${CHASSIS},) 239398841eSJiafei Pan$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS})) 249398841eSJiafei Panendif 259398841eSJiafei Pan 269398841eSJiafei Panifneq (${PLAT_DDR_PHY},) 279398841eSJiafei Pan$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY})) 289398841eSJiafei Panendif 299398841eSJiafei Pan 309398841eSJiafei Panifneq (${PHYS_SYS},) 319398841eSJiafei Pan$(eval $(call add_define,CONFIG_PHYS_64BIT)) 329398841eSJiafei Panendif 339398841eSJiafei Pan 349398841eSJiafei Panifneq (${CSF_HDR_SZ},) 359398841eSJiafei Pan$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ})) 369398841eSJiafei Panendif 379398841eSJiafei Pan 389398841eSJiafei Panifneq (${OCRAM_START_ADDR},) 399398841eSJiafei Pan$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR})) 409398841eSJiafei Panendif 419398841eSJiafei Pan 429398841eSJiafei Panifneq (${OCRAM_SIZE},) 439398841eSJiafei Pan$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE})) 449398841eSJiafei Panendif 459398841eSJiafei Pan 469398841eSJiafei Panifneq (${NXP_ROM_RSVD},) 479398841eSJiafei Pan$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD})) 489398841eSJiafei Panendif 499398841eSJiafei Pan 509398841eSJiafei Panifneq (${BL2_BASE},) 519398841eSJiafei Pan$(eval $(call add_define_val,BL2_BASE,${BL2_BASE})) 529398841eSJiafei Panendif 539398841eSJiafei Pan 549398841eSJiafei Panifeq (${SEC_MEM_NON_COHERENT},yes) 559398841eSJiafei Pan$(eval $(call add_define,SEC_MEM_NON_COHERENT)) 569398841eSJiafei Panendif 579398841eSJiafei Pan 589398841eSJiafei Panifneq (${NXP_ESDHC_ENDIANNESS},) 599398841eSJiafei Pan$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS})) 609398841eSJiafei Panendif 619398841eSJiafei Pan 629398841eSJiafei Panifneq (${NXP_SFP_VER},) 639398841eSJiafei Pan$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER})) 649398841eSJiafei Panendif 659398841eSJiafei Pan 669398841eSJiafei Panifneq (${NXP_SFP_ENDIANNESS},) 679398841eSJiafei Pan$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS})) 689398841eSJiafei Panendif 699398841eSJiafei Pan 709398841eSJiafei Panifneq (${NXP_GPIO_ENDIANNESS},) 719398841eSJiafei Pan$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS})) 729398841eSJiafei Panendif 739398841eSJiafei Pan 749398841eSJiafei Panifneq (${NXP_SNVS_ENDIANNESS},) 759398841eSJiafei Pan$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS})) 769398841eSJiafei Panendif 779398841eSJiafei Pan 789398841eSJiafei Panifneq (${NXP_GUR_ENDIANNESS},) 799398841eSJiafei Pan$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS})) 809398841eSJiafei Panendif 819398841eSJiafei Pan 829398841eSJiafei Panifneq (${NXP_FSPI_ENDIANNESS},) 839398841eSJiafei Pan$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS})) 849398841eSJiafei Panendif 859398841eSJiafei Pan 869398841eSJiafei Panifneq (${NXP_SEC_ENDIANNESS},) 879398841eSJiafei Pan$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS})) 889398841eSJiafei Panendif 899398841eSJiafei Pan 909398841eSJiafei Panifneq (${NXP_DDR_ENDIANNESS},) 919398841eSJiafei Pan$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS})) 929398841eSJiafei Panendif 939398841eSJiafei Pan 949398841eSJiafei Panifneq (${NXP_QSPI_ENDIANNESS},) 959398841eSJiafei Pan$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS})) 969398841eSJiafei Panendif 979398841eSJiafei Pan 989398841eSJiafei Panifneq (${NXP_SCFG_ENDIANNESS},) 999398841eSJiafei Pan$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS})) 1009398841eSJiafei Panendif 1019398841eSJiafei Pan 1029398841eSJiafei Panifneq (${NXP_IFC_ENDIANNESS},) 1039398841eSJiafei Pan$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS})) 1049398841eSJiafei Panendif 1059398841eSJiafei Pan 1069398841eSJiafei Panifneq (${NXP_DDR_INTLV_256B},) 1079398841eSJiafei Pan$(eval $(call add_define,NXP_DDR_INTLV_256B)) 1089398841eSJiafei Panendif 1099398841eSJiafei Pan 1109398841eSJiafei Panifneq (${PLAT_XLAT_TABLES_DYNAMIC},) 1119398841eSJiafei Pan$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) 1129398841eSJiafei Panendif 11310b1e13bSJiafei Pan 11410b1e13bSJiafei Panifeq (${OCRAM_ECC_EN},yes) 11510b1e13bSJiafei Pan$(eval $(call add_define,CONFIG_OCRAM_ECC_EN)) 11610b1e13bSJiafei Paninclude ${PLAT_COMMON_PATH}/ocram/ocram.mk 11710b1e13bSJiafei Panendif 118