1*9df5ba05SJiafei Pan# 2*9df5ba05SJiafei Pan# Copyright 2022 NXP 3*9df5ba05SJiafei Pan# 4*9df5ba05SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 5*9df5ba05SJiafei Pan# 6*9df5ba05SJiafei Pan# 7*9df5ba05SJiafei Pan#------------------------------------------------------------------------------ 8*9df5ba05SJiafei Pan# 9*9df5ba05SJiafei Pan# This file contains the basic architecture definitions that drive the build 10*9df5ba05SJiafei Pan# 11*9df5ba05SJiafei Pan# ----------------------------------------------------------------------------- 12*9df5ba05SJiafei Pan 13*9df5ba05SJiafei PanCORE_TYPE := a53 14*9df5ba05SJiafei Pan 15*9df5ba05SJiafei PanCACHE_LINE := 6 16*9df5ba05SJiafei Pan 17*9df5ba05SJiafei Pan# Set to GIC400 or GIC500 18*9df5ba05SJiafei PanGIC := GIC500 19*9df5ba05SJiafei Pan 20*9df5ba05SJiafei Pan# Set to CCI400 or CCN504 or CCN508 21*9df5ba05SJiafei PanINTERCONNECT := CCI400 22*9df5ba05SJiafei Pan 23*9df5ba05SJiafei Pan# Select the DDR PHY generation to be used 24*9df5ba05SJiafei PanPLAT_DDR_PHY := PHY_GEN1 25*9df5ba05SJiafei Pan 26*9df5ba05SJiafei PanPHYS_SYS := 64 27*9df5ba05SJiafei Pan 28*9df5ba05SJiafei Pan# Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 29*9df5ba05SJiafei PanCHASSIS := 3 30*9df5ba05SJiafei Pan 31*9df5ba05SJiafei Pan# TZC IP Details TZC used is TZC380 or TZC400 32*9df5ba05SJiafei PanTZC_ID := TZC400 33*9df5ba05SJiafei Pan 34*9df5ba05SJiafei Pan# CONSOLE Details available is NS16550 or PL011 35*9df5ba05SJiafei PanCONSOLE := NS16550 36*9df5ba05SJiafei Pan 37*9df5ba05SJiafei PanNXP_SFP_VER := 3_4 38*9df5ba05SJiafei Pan 39*9df5ba05SJiafei Pan# In IMAGE_BL2, compile time flag for handling Cache coherency 40*9df5ba05SJiafei Pan# with CAAM for BL2 running from OCRAM 41*9df5ba05SJiafei PanSEC_MEM_NON_COHERENT := yes 42*9df5ba05SJiafei Pan 43*9df5ba05SJiafei Pan 44*9df5ba05SJiafei Pan# OCRAM MAP for BL2 45*9df5ba05SJiafei Pan# Before BL2 46*9df5ba05SJiafei Pan# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables) 47*9df5ba05SJiafei Pan# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB) 48*9df5ba05SJiafei Pan# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB) 49*9df5ba05SJiafei PanOCRAM_START_ADDR := 0x18000000 50*9df5ba05SJiafei PanOCRAM_SIZE := 0x20000 51*9df5ba05SJiafei Pan 52*9df5ba05SJiafei PanCSF_HDR_SZ := 0x3000 53*9df5ba05SJiafei Pan 54*9df5ba05SJiafei Pan# Area of OCRAM reserved by ROM code 55*9df5ba05SJiafei PanNXP_ROM_RSVD := 0xa000 56*9df5ba05SJiafei Pan 57*9df5ba05SJiafei Pan# Input to CST create_hdr_isbc tool 58*9df5ba05SJiafei PanBL2_HDR_LOC := 0x1801D000 59*9df5ba05SJiafei Pan 60*9df5ba05SJiafei Pan# Location of BL2 on OCRAM 61*9df5ba05SJiafei Pan# BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD 62*9df5ba05SJiafei PanBL2_BASE := 0x1800a000 63*9df5ba05SJiafei Pan 64*9df5ba05SJiafei Pan# SoC ERRATUM to be enabled 65*9df5ba05SJiafei Pan 66*9df5ba05SJiafei Pan# ARM Erratum 67*9df5ba05SJiafei PanERRATA_A53_855873 := 1 68*9df5ba05SJiafei Pan 69*9df5ba05SJiafei Pan# DDR Erratum 70*9df5ba05SJiafei PanERRATA_DDR_A008511 := 1 71*9df5ba05SJiafei PanERRATA_DDR_A009803 := 1 72*9df5ba05SJiafei PanERRATA_DDR_A009942 := 1 73*9df5ba05SJiafei PanERRATA_DDR_A010165 := 1 74*9df5ba05SJiafei Pan 75*9df5ba05SJiafei Pan# Define Endianness of each module 76*9df5ba05SJiafei PanNXP_ESDHC_ENDIANNESS := LE 77*9df5ba05SJiafei PanNXP_SFP_ENDIANNESS := LE 78*9df5ba05SJiafei PanNXP_GPIO_ENDIANNESS := LE 79*9df5ba05SJiafei PanNXP_SNVS_ENDIANNESS := LE 80*9df5ba05SJiafei PanNXP_GUR_ENDIANNESS := LE 81*9df5ba05SJiafei PanNXP_SEC_ENDIANNESS := LE 82*9df5ba05SJiafei PanNXP_DDR_ENDIANNESS := LE 83*9df5ba05SJiafei PanNXP_QSPI_ENDIANNESS := LE 84*9df5ba05SJiafei Pan 85*9df5ba05SJiafei Pan# OCRAM ECC Enabled 86*9df5ba05SJiafei PanOCRAM_ECC_EN := yes 87