xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision dfdb73f77317b1349e383c5836454db67f8643d3) 
1/*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL2_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL2_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        ASSERT(. == ALIGN(PAGE_SIZE),
29        ".text address is not aligned on a page boundary.");
30
31        __TEXT_START__ = .;
32
33        *bl2_entrypoint.o(.text*)
34
35        *(SORT_BY_ALIGNMENT(.text*))
36        *(.vectors)
37        __TEXT_END_UNALIGNED__ = .;
38
39        . = ALIGN(PAGE_SIZE);
40
41        __TEXT_END__ = .;
42    } >RAM
43
44    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
45    .ARM.extab . : {
46        *(.ARM.extab* .gnu.linkonce.armextab.*)
47    } >RAM
48
49    .ARM.exidx . : {
50        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
51    } >RAM
52
53    .rodata . : {
54        __RODATA_START__ = .;
55
56        *(SORT_BY_ALIGNMENT(.rodata*))
57
58        RODATA_COMMON
59
60        __RODATA_END_UNALIGNED__ = .;
61        . = ALIGN(PAGE_SIZE);
62
63        __RODATA_END__ = .;
64    } >RAM
65#else /* SEPARATE_CODE_AND_RODATA */
66    .ro . : {
67        ASSERT(. == ALIGN(PAGE_SIZE),
68        ".ro address is not aligned on a page boundary.");
69
70        __RO_START__ = .;
71
72        *bl2_entrypoint.o(.text*)
73        *(SORT_BY_ALIGNMENT(.text*))
74        *(SORT_BY_ALIGNMENT(.rodata*))
75
76        RODATA_COMMON
77
78        *(.vectors)
79
80        __RO_END_UNALIGNED__ = .;
81
82        /*
83         * Memory page(s) mapped to this section will be marked as read-only,
84         * executable. No RW data from the next section must creep in. Ensure
85         * that the rest of the current memory page is unused.
86         */
87        . = ALIGN(PAGE_SIZE);
88
89        __RO_END__ = .;
90    } >RAM
91#endif /* SEPARATE_CODE_AND_RODATA */
92
93    __RW_START__ = .;
94
95    DATA_SECTION >RAM
96    STACK_SECTION >RAM
97    BSS_SECTION >RAM
98    XLAT_TABLE_SECTION >RAM
99
100#if USE_COHERENT_MEM
101    /*
102     * The base address of the coherent memory section must be page-aligned to
103     * guarantee that the coherent data are stored on their own pages and are
104     * not mixed with normal data.  This is required to set up the correct
105     * memory attributes for the coherent data page tables.
106     */
107    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
108        __COHERENT_RAM_START__ = .;
109        *(.tzfw_coherent_mem)
110        __COHERENT_RAM_END_UNALIGNED__ = .;
111
112        /*
113         * Memory page(s) mapped to this section will be marked as device
114         * memory. No other unexpected data must creep in. Ensure the rest of
115         * the current memory page is unused.
116         */
117        . = ALIGN(PAGE_SIZE);
118
119        __COHERENT_RAM_END__ = .;
120    } >RAM
121#endif /* USE_COHERENT_MEM */
122
123    __RW_END__ = .;
124    __BL2_END__ = .;
125    RAM_REGION_END = .;
126
127    __BSS_SIZE__ = SIZEOF(.bss);
128
129#if USE_COHERENT_MEM
130    __COHERENT_RAM_UNALIGNED_SIZE__ =
131        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
132#endif /* USE_COHERENT_MEM */
133
134    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
135}
136