1*2771dd02SJiafei Pan /* 2*2771dd02SJiafei Pan * Copyright 2022 NXP 3*2771dd02SJiafei Pan * 4*2771dd02SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*2771dd02SJiafei Pan */ 6*2771dd02SJiafei Pan 7*2771dd02SJiafei Pan #ifndef PLAT_DEF_H 8*2771dd02SJiafei Pan #define PLAT_DEF_H 9*2771dd02SJiafei Pan 10*2771dd02SJiafei Pan #include <arch.h> 11*2771dd02SJiafei Pan /* 12*2771dd02SJiafei Pan * Required without TBBR. 13*2771dd02SJiafei Pan * To include the defines for DDR PHY 14*2771dd02SJiafei Pan * Images. 15*2771dd02SJiafei Pan */ 16*2771dd02SJiafei Pan #include <tbbr_img_def.h> 17*2771dd02SJiafei Pan 18*2771dd02SJiafei Pan #include <policy.h> 19*2771dd02SJiafei Pan #include <soc.h> 20*2771dd02SJiafei Pan 21*2771dd02SJiafei Pan #define NXP_SPD_EEPROM0 0x51 22*2771dd02SJiafei Pan 23*2771dd02SJiafei Pan #define NXP_SYSCLK_FREQ 100000000 24*2771dd02SJiafei Pan #define NXP_DDRCLK_FREQ 100000000 25*2771dd02SJiafei Pan 26*2771dd02SJiafei Pan /* UART related definition */ 27*2771dd02SJiafei Pan #define NXP_CONSOLE_ADDR NXP_UART_ADDR 28*2771dd02SJiafei Pan #define NXP_CONSOLE_BAUDRATE 115200 29*2771dd02SJiafei Pan 30*2771dd02SJiafei Pan /* Size of cacheable stacks */ 31*2771dd02SJiafei Pan #if defined(IMAGE_BL2) 32*2771dd02SJiafei Pan #if defined(TRUSTED_BOARD_BOOT) 33*2771dd02SJiafei Pan #define PLATFORM_STACK_SIZE 0x2000 34*2771dd02SJiafei Pan #else 35*2771dd02SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 36*2771dd02SJiafei Pan #endif 37*2771dd02SJiafei Pan #elif defined(IMAGE_BL31) 38*2771dd02SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 39*2771dd02SJiafei Pan #endif 40*2771dd02SJiafei Pan 41*2771dd02SJiafei Pan #define BL2_START NXP_OCRAM_ADDR 42*2771dd02SJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 43*2771dd02SJiafei Pan #define BL2_NOLOAD_START NXP_OCRAM_ADDR 44*2771dd02SJiafei Pan #define BL2_NOLOAD_LIMIT BL2_BASE 45*2771dd02SJiafei Pan 46*2771dd02SJiafei Pan /* IO defines as needed by IO driver framework */ 47*2771dd02SJiafei Pan #define MAX_IO_DEVICES 4 48*2771dd02SJiafei Pan #define MAX_IO_BLOCK_DEVICES 1 49*2771dd02SJiafei Pan #define MAX_IO_HANDLES 4 50*2771dd02SJiafei Pan 51*2771dd02SJiafei Pan /* 52*2771dd02SJiafei Pan * FIP image defines - Offset at which FIP Image would be present 53*2771dd02SJiafei Pan * Image would include Bl31 , Bl33 and Bl32 (optional) 54*2771dd02SJiafei Pan */ 55*2771dd02SJiafei Pan #ifdef POLICY_FUSE_PROVISION 56*2771dd02SJiafei Pan #define MAX_FIP_DEVICES 2 57*2771dd02SJiafei Pan #endif 58*2771dd02SJiafei Pan 59*2771dd02SJiafei Pan #ifndef MAX_FIP_DEVICES 60*2771dd02SJiafei Pan #define MAX_FIP_DEVICES 1 61*2771dd02SJiafei Pan #endif 62*2771dd02SJiafei Pan 63*2771dd02SJiafei Pan #define BL32_IRQ_SEC_PHY_TIMER 29 64*2771dd02SJiafei Pan #define BL31_WDOG_SEC 89 65*2771dd02SJiafei Pan 66*2771dd02SJiafei Pan /* 67*2771dd02SJiafei Pan * ID of the secure physical generic timer interrupt used by the BL32. 68*2771dd02SJiafei Pan */ 69*2771dd02SJiafei Pan #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 70*2771dd02SJiafei Pan INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 71*2771dd02SJiafei Pan GIC_INTR_CFG_LEVEL) 72*2771dd02SJiafei Pan 73*2771dd02SJiafei Pan /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 74*2771dd02SJiafei Pan #define PLAT_LS_G0_IRQ_PROPS(grp) \ 75*2771dd02SJiafei Pan INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 76*2771dd02SJiafei Pan GIC_INTR_CFG_EDGE), \ 77*2771dd02SJiafei Pan INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ 78*2771dd02SJiafei Pan GIC_INTR_CFG_LEVEL) 79*2771dd02SJiafei Pan 80*2771dd02SJiafei Pan #endif /* PLAT_DEF_H */ 81