19d250f03SJiafei Pan# 29d250f03SJiafei Pan# Copyright 2018-2021 NXP 39d250f03SJiafei Pan# 49d250f03SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 59d250f03SJiafei Pan# 69d250f03SJiafei Pan# 79d250f03SJiafei Pan#------------------------------------------------------------------------------ 89d250f03SJiafei Pan# 99d250f03SJiafei Pan# This file contains the basic architecture definitions that drive the build 109d250f03SJiafei Pan# 119d250f03SJiafei Pan# ----------------------------------------------------------------------------- 129d250f03SJiafei Pan 139d250f03SJiafei PanCORE_TYPE := a72 149d250f03SJiafei Pan 159d250f03SJiafei PanCACHE_LINE := 6 169d250f03SJiafei Pan 179d250f03SJiafei Pan# Set to GIC400 or GIC500 189d250f03SJiafei PanGIC := GIC500 199d250f03SJiafei Pan 209d250f03SJiafei Pan# Set to CCI400 or CCN504 or CCN508 219d250f03SJiafei PanINTERCONNECT := CCI400 229d250f03SJiafei Pan 239d250f03SJiafei Pan# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 249d250f03SJiafei PanCHASSIS := 3_2 259d250f03SJiafei Pan 269d250f03SJiafei Pan# TZC used is TZC380 or TZC400 279d250f03SJiafei PanTZC_ID := TZC400 289d250f03SJiafei Pan 299d250f03SJiafei Pan# CONSOLE is NS16550 or PL011 309d250f03SJiafei PanCONSOLE := NS16550 319d250f03SJiafei Pan 329d250f03SJiafei Pan# DDR PHY generation to be used 339d250f03SJiafei PanPLAT_DDR_PHY := PHY_GEN1 349d250f03SJiafei Pan 359d250f03SJiafei PanPHYS_SYS := 64 369d250f03SJiafei Pan 379d250f03SJiafei Pan# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 389d250f03SJiafei Pan# Input to CST create_hdr_esbc tool 399d250f03SJiafei PanCSF_HDR_SZ := 0x3000 409d250f03SJiafei Pan 419d250f03SJiafei Pan# In IMAGE_BL2, compile time flag for handling Cache coherency 429d250f03SJiafei Pan# with CAAM for BL2 running from OCRAM 439d250f03SJiafei PanSEC_MEM_NON_COHERENT := yes 449d250f03SJiafei Pan 459d250f03SJiafei Pan# OCRAM MAP for BL2 469d250f03SJiafei Pan# Before BL2 479d250f03SJiafei Pan# 0x18000000 - 0x18009fff -> Used by ROM code 489d250f03SJiafei Pan# 0x1800a000 - 0x1800dfff -> CSF header for BL2 499d250f03SJiafei Pan# For FlexSFlexSPI boot 509d250f03SJiafei Pan# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 519d250f03SJiafei Pan# For SD boot 529d250f03SJiafei Pan# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 539d250f03SJiafei Pan# 0x18030000 - 0x18040000 -> Reserved for SD buffer 549d250f03SJiafei PanOCRAM_START_ADDR := 0x18000000 559d250f03SJiafei PanOCRAM_SIZE := 0x40000 569d250f03SJiafei Pan 579d250f03SJiafei Pan# Area of OCRAM reserved by ROM code 589d250f03SJiafei PanNXP_ROM_RSVD := 0xa000 599d250f03SJiafei Pan 609d250f03SJiafei Pan# Location of BL2 on OCRAM 619d250f03SJiafei PanBL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 629d250f03SJiafei Pan 639d250f03SJiafei Pan# Covert to HEX to be used by create_pbl.mk 649d250f03SJiafei PanBL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 659d250f03SJiafei Pan 669d250f03SJiafei Pan# BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD) 679d250f03SJiafei Pan# This value BL2_HDR_LOC + CSF_HDR_SZ should not 689d250f03SJiafei Pan# overalp with BL2_BASE 699d250f03SJiafei Pan# Input to CST create_hdr_isbc tool 709d250f03SJiafei PanBL2_HDR_LOC := 0x1800A000 719d250f03SJiafei Pan 729d250f03SJiafei Pan# SoC ERRATAS to be enabled 739d250f03SJiafei Pan 74*c45791b2SJiafei Pan# DDR ERRATA 759d250f03SJiafei PanERRATA_DDR_A009803 := 1 769d250f03SJiafei PanERRATA_DDR_A009942 := 1 779d250f03SJiafei PanERRATA_DDR_A010165 := 1 789d250f03SJiafei Pan 799d250f03SJiafei Pan# Enable dynamic memory mapping 809d250f03SJiafei PanPLAT_XLAT_TABLES_DYNAMIC := 1 819d250f03SJiafei Pan 829d250f03SJiafei Pan# Define Endianness of each module 839d250f03SJiafei PanNXP_GUR_ENDIANNESS := LE 849d250f03SJiafei PanNXP_DDR_ENDIANNESS := LE 859d250f03SJiafei PanNXP_SEC_ENDIANNESS := LE 869d250f03SJiafei PanNXP_SFP_ENDIANNESS := LE 879d250f03SJiafei PanNXP_SNVS_ENDIANNESS := LE 889d250f03SJiafei PanNXP_ESDHC_ENDIANNESS := LE 899d250f03SJiafei PanNXP_QSPI_ENDIANNESS := LE 909d250f03SJiafei PanNXP_FSPI_ENDIANNESS := LE 912475f63bSJiafei PanNXP_SCFG_ENDIANNESS := LE 922475f63bSJiafei PanNXP_GPIO_ENDIANNESS := LE 939d250f03SJiafei Pan 949d250f03SJiafei PanNXP_SFP_VER := 3_4 959d250f03SJiafei Pan 969d250f03SJiafei Pan# OCRAM ECC Enabled 979d250f03SJiafei PanOCRAM_ECC_EN := yes 98