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Searched refs:BIT_32 (Results 1 – 25 of 62) sorted by relevance

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/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp2_pwr.h72 #define PWR_CR1_VDDIO3VMEN BIT_32(0)
73 #define PWR_CR1_VDDIO4VMEN BIT_32(1)
74 #define PWR_CR1_USB33VMEN BIT_32(2)
75 #define PWR_CR1_UCPDVMEN BIT_32(3)
76 #define PWR_CR1_AVMEN BIT_32(4)
77 #define PWR_CR1_VDDIO3SV BIT_32(8)
78 #define PWR_CR1_VDDIO4SV BIT_32(9)
79 #define PWR_CR1_USB33SV BIT_32(10)
80 #define PWR_CR1_UCPDSV BIT_32(11)
81 #define PWR_CR1_ASV BIT_32(12)
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H A Dbsec3_reg.h41 #define BSEC_OTPCR_PROG BIT_32(13)
42 #define BSEC_OTPCR_PPLOCK BIT_32(14)
47 #define BSEC_LOCKR_GWLOCK_MASK BIT_32(0)
49 #define BSEC_LOCKR_DENLOCK_MASK BIT_32(1)
51 #define BSEC_LOCKR_HKLOCK_MASK BIT_32(2)
55 #define BSEC_DENR_LPDBGEN BIT_32(0)
56 #define BSEC_DENR_DBGENA BIT_32(1)
57 #define BSEC_DENR_NIDENA BIT_32(2)
58 #define BSEC_DENR_DEVICEEN BIT_32(3)
59 #define BSEC_DENR_HDPEN BIT_32(4)
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H A Dstm32mp2_risaf.h22 #define _RISAF_CR_GLOCK BIT_32(0)
24 #define _RISAF_SR_KEYVALID BIT_32(0)
25 #define _RISAF_SR_KEYRDY BIT_32(1)
26 #define _RISAF_SR_ENCDIS BIT_32(2)
53 #define _RISAF_REG_CFGR_BREN BIT_32(_RISAF_REG_CFGR_BREN_SHIFT)
55 #define _RISAF_REG_CFGR_SEC BIT_32(_RISAF_REG_CFGR_SEC_SHIFT)
57 #define _RISAF_REG_CFGR_ENC BIT_32(_RISAF_REG_CFGR_ENC_SHIFT)
74 #define DT_RISAF_EN_MASK BIT_32(DT_RISAF_EN_SHIFT)
76 #define DT_RISAF_SEC_MASK BIT_32(DT_RISAF_SEC_SHIFT)
78 #define DT_RISAF_ENC_MASK BIT_32(DT_RISAF_ENC_SHIFT)
H A Dstm32mp_rifsc_regs.h29 #define RIFSC_RIMC_ATTRx_CIDSEL BIT_32(2)
32 #define RIFSC_RIMC_ATTRx_MSEC BIT_32(8)
33 #define RIFSC_RIMC_ATTRx_MPRIV BIT_32(9)
37 #define _RIFSC_CIDCFGR_CFEN BIT_32(0)
38 #define _RIFSC_CIDCFGR_SEM_EN BIT_32(1)
45 #define _RIFSC_SEMCR_SEM_MUTEX BIT_32(0)
/rk3399_ARM-atf/drivers/st/usb_dwc3/
H A Dusb_dwc3_regs.h81 #define _DWC3_GSBUSCFG0_INCRBRSTENA BIT_32(0)
82 #define _DWC3_GSBUSCFG0_INCR4BRSTENA BIT_32(1)
83 #define _DWC3_GSBUSCFG0_INCR8BRSTENA BIT_32(2)
84 #define _DWC3_GSBUSCFG0_INCR16BRSTENA BIT_32(3)
85 #define _DWC3_GSBUSCFG0_INCR32BRSTENA BIT_32(4)
86 #define _DWC3_GSBUSCFG0_INCR64BRSTENA BIT_32(5)
87 #define _DWC3_GSBUSCFG0_INCR128BRSTENA BIT_32(6)
88 #define _DWC3_GSBUSCFG0_INCR256BRSTENA BIT_32(7)
89 #define _DWC3_GSBUSCFG0_DESBIGEND BIT_32(10)
90 #define _DWC3_GSBUSCFG0_DATBIGEND BIT_32(11)
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/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.h38 #define XFERTYPE_DPSEL BIT_32(21U)
39 #define XFERTYPE_CICEN BIT_32(20U)
40 #define XFERTYPE_CCCEN BIT_32(19U)
41 #define XFERTYPE_RSPTYP_136 BIT_32(16U)
42 #define XFERTYPE_RSPTYP_48 BIT_32(17U)
43 #define XFERTYPE_RSPTYP_48_BUSY (BIT_32(16U) | BIT_32(17U))
46 #define PSTATE_DAT0 BIT_32(24U)
47 #define PSTATE_SDSTB BIT_32(3U)
48 #define PSTATE_DLA BIT_32(2U)
49 #define PSTATE_CDIHB BIT_32(1U)
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/rk3399_ARM-atf/plat/amd/versal2/include/
H A Dplat_ipi.h68 #define IPI0_TRIG_BIT BIT_32(2)
69 #define PMC_IPI_TRIG_BIT BIT_32(1)
71 #define IPI1_TRIG_BIT BIT_32(3)
73 #define IPI2_TRIG_BIT BIT_32(4)
75 #define IPI3_TRIG_BIT BIT_32(5)
77 #define IPI4_TRIG_BIT BIT_32(6)
79 #define IPI5_TRIG_BIT BIT_32(7)
82 #define PMC_NOBUF_TRIG_BIT BIT_32(8)
84 #define IPI6_NOBUF_95_TRIG_BIT BIT_32(9)
86 #define IPI1_NOBUF_TRIG_BIT BIT_32(10)
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/rk3399_ARM-atf/plat/qti/msm8916/
H A Dmsm8916_cpu_boot.c17 #define CPU_PWR_CTL_CLAMP BIT_32(0)
18 #define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1)
19 #define CPU_PWR_CTL_L1_RST_DIS BIT_32(2)
20 #define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3)
21 #define CPU_PWR_CTL_CORE_RST BIT_32(4)
22 #define CPU_PWR_CTL_COREPOR_RST BIT_32(5)
23 #define CPU_PWR_CTL_GATE_CLK BIT_32(6)
24 #define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7)
26 #define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
34 #define PWR_CTL_OVERRIDE_PRESETDBG BIT_32(22)
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H A Dmsm8916_config.c42 #define APCS_GLB_SECURE_STS_NS BIT_32(0)
43 #define APCS_GLB_SECURE_PWR_NS BIT_32(1)
50 #define REMAP_EN BIT_32(0)
119 #define CLK_OFF BIT_32(31)
125 #define APSS_TCU_CLK_ENA BIT_32(1)
126 #define GFX_TCU_CLK_ENA BIT_32(2)
127 #define GFX_TBU_CLK_ENA BIT_32(3)
128 #define SMMU_CFG_CLK_ENA BIT_32(12)
133 #define SMMU_SACR_CACHE_LOCK BIT_32(26)
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/
H A Ds32cc-clk-regs.h25 #define FXOSC_CTRL_OSC_BYP BIT_32(31U)
26 #define FXOSC_CTRL_COMP_EN BIT_32(24U)
35 #define FXOSC_CTRL_OSCON BIT_32(0U)
38 #define FXOSC_STAT_OSC_STAT BIT_32(31U)
42 #define PLLDIG_PLLCR_PLLPD BIT_32(31U)
45 #define PLLDIG_PLLSR_LOCK BIT_32(2U)
58 #define PLLDIG_PLLFD_SMDEN BIT_32(30U)
65 #define PLLDIG_PLLODIV_DE BIT_32(31U)
79 #define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U)
80 #define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U)
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/rk3399_ARM-atf/include/drivers/arm/fvp/
H A Dfvp_pwrc.h17 #define PWKUPR_WEN BIT_32(31)
19 #define PSYSR_AFF_L2 BIT_32(31)
20 #define PSYSR_AFF_L1 BIT_32(30)
21 #define PSYSR_AFF_L0 BIT_32(29)
22 #define PSYSR_WEN BIT_32(28)
23 #define PSYSR_PC BIT_32(27)
24 #define PSYSR_PP BIT_32(26)
/rk3399_ARM-atf/include/drivers/
H A Dmmc.h22 #define OCR_POWERUP BIT_32(31U)
23 #define OCR_HCS BIT_32(30U)
27 #define OCR_3_5_3_6 BIT_32(23U)
28 #define OCR_3_4_3_5 BIT_32(22U)
29 #define OCR_3_3_3_4 BIT_32(21U)
30 #define OCR_3_2_3_3 BIT_32(20U)
31 #define OCR_3_1_3_2 BIT_32(19U)
32 #define OCR_3_0_3_1 BIT_32(18U)
33 #define OCR_2_9_3_0 BIT_32(17U)
34 #define OCR_2_8_2_9 BIT_32(16U)
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H A Dconsole.h26 #define CONSOLE_FLAG_BOOT BIT_32(0)
27 #define CONSOLE_FLAG_RUNTIME BIT_32(1)
28 #define CONSOLE_FLAG_CRASH BIT_32(2)
32 #define CONSOLE_FLAG_TRANSLATE_CRLF BIT_32(8)
/rk3399_ARM-atf/include/drivers/arm/
H A Dgicv3.h132 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
133 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
134 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
135 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
136 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
137 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
138 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
197 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
200 #define GICR_CTLR_DPG1S_BIT BIT_32(GICR_CTLR_DPG1S_SHIFT)
203 #define GICR_CTLR_DPG1NS_BIT BIT_32(GICR_CTLR_DPG1NS_SHIFT)
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H A Dgicv2.h82 #define EOI_MODE_NS BIT_32(10)
83 #define EOI_MODE_S BIT_32(9)
84 #define IRQ_BYP_DIS_GRP1 BIT_32(8)
85 #define FIQ_BYP_DIS_GRP1 BIT_32(7)
86 #define IRQ_BYP_DIS_GRP0 BIT_32(6)
87 #define FIQ_BYP_DIS_GRP0 BIT_32(5)
88 #define CBPR BIT_32(4)
90 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
91 #define ACK_CTL BIT_32(2)
125 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
H A Dcci.h70 #define DVM_EN_BIT BIT_32(1)
71 #define SNOOP_EN_BIT BIT_32(0)
72 #define SUPPORT_SNOOPS BIT_32(30)
73 #define SUPPORT_DVM BIT_32(31)
76 #define CHANGE_PENDING_BIT BIT_32(0)
H A Dtzc380.h45 #define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
46 #define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
60 #define TZC_SP_NS_W BIT_32(0)
61 #define TZC_SP_NS_R BIT_32(1)
62 #define TZC_SP_S_W BIT_32(2)
63 #define TZC_SP_S_R BIT_32(3)
/rk3399_ARM-atf/include/dt-bindings/soc/
H A Drif.h23 #define RIF_CID0_BF BIT_32(RIF_CID0)
24 #define RIF_CID1_BF BIT_32(RIF_CID1)
25 #define RIF_CID2_BF BIT_32(RIF_CID2)
26 #define RIF_CID3_BF BIT_32(RIF_CID3)
27 #define RIF_CID4_BF BIT_32(RIF_CID4)
28 #define RIF_CID5_BF BIT_32(RIF_CID5)
29 #define RIF_CID6_BF BIT_32(RIF_CID6)
30 #define RIF_CID7_BF BIT_32(RIF_CID7)
/rk3399_ARM-atf/drivers/nxp/console/
H A Dlinflex_console.S16 #define LINCR1_INIT BIT_32(0)
17 #define LINCR1_MME BIT_32(4)
25 #define UARTCR_ROSE BIT_32(23)
33 #define UARTCR_UART BIT_32(0)
34 #define UARTCR_WL0 BIT_32(1)
35 #define UARTCR_PC0 BIT_32(3)
36 #define UARTCR_TXEN BIT_32(4)
37 #define UARTCR_RXEN BIT_32(5)
38 #define UARTCR_PC1 BIT_32(6)
39 #define UARTCR_TFBM BIT_32(8)
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/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Dmc_me.c25 #define MC_ME_PRTN_N_PCE BIT_32(0)
26 #define MC_ME_PRTN_N_OSSE BIT_32(2)
28 #define MC_ME_PRTN_N_PCUD BIT_32(0)
29 #define MC_ME_PRTN_N_OSSUD BIT_32(2)
31 #define MC_ME_PRTN_N_PCS BIT_32(0)
36 #define MC_ME_PRTN_N_REQ(PART) BIT_32(PART)
39 #define RDC_CTRL_UNLOCK BIT_32(31)
40 #define RDC_RD_INTERCONNECT_DISABLE BIT_32(3)
44 BIT_32(4)
/rk3399_ARM-atf/services/std_svc/sdei/
H A Dsdei_private.h100 return ((map->map_flags & BIT_32(SDEI_MAPF_PRIVATE_SHIFT_)) != 0U); in is_event_private()
110 return ((map->map_flags & BIT_32(SDEI_MAPF_CRITICAL_SHIFT_)) != 0U); in is_event_critical()
120 return ((map->map_flags & BIT_32(SDEI_MAPF_SIGNALABLE_SHIFT_)) != 0U); in is_event_signalable()
125 return ((map->map_flags & BIT_32(SDEI_MAPF_DYNAMIC_SHIFT_)) != 0U); in is_map_dynamic()
136 return ((map->map_flags & BIT_32(SDEI_MAPF_BOUND_SHIFT_)) != 0U); in is_map_bound()
141 map->map_flags |= BIT_32(SDEI_MAPF_BOUND_SHIFT_); in set_map_bound()
146 return ((map->map_flags & BIT_32(SDEI_MAPF_EXPLICIT_SHIFT_)) != 0U); in is_map_explicit()
151 map->map_flags &= ~BIT_32(SDEI_MAPF_BOUND_SHIFT_); in clr_map_bound()
181 return ((se->state & BIT_32(bit_no)) != 0U); in get_ev_state_bit()
186 se->state &= ~BIT_32(bit_no); in clr_ev_state_bit()
/rk3399_ARM-atf/include/plat/arm/board/common/
H A Dv2m_def.h31 #define V2M_CFGCTRL_START BIT_32(31)
32 #define V2M_CFGCTRL_RW BIT_32(30)
106 #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
107 #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
108 #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
109 #define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
/rk3399_ARM-atf/plat/allwinner/sun50i_a64/
H A Dsunxi_power.c46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
47 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
53 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc()
62 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc()
238 code[0] = (code[0] & ~0xffff) | BIT_32(core); in sunxi_cpu_power_off_self()
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/
H A Ds32cc-ncore.h27 #define NCORE_DIRUSFE_SFEN(SF) BIT_32(SF)
31 #define NCORE_DIRUCASE_CASNPEN(CAIU) BIT_32(CAIU)
40 #define NCORE_DIRUSFMA_MNTOPACTV BIT_32(0)
54 #define NCORE_CAIUTC_ISOLEN_MASK BIT_32(NCORE_CAIUTC_ISOLEN_SHIFT)
70 #define NCORE_CSADSE_DVMSNPEN(CAIU) BIT_32(CAIU)
/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicdv2_helpers.c260 gicd_write_igroupr(base, id, reg_val | BIT_32(bit_num)); in gicd_set_igroupr()
268 gicd_write_igroupr(base, id, reg_val & ~BIT_32(bit_num)); in gicd_clr_igroupr()
275 gicd_write_isenabler(base, id, BIT_32(bit_num)); in gicd_set_isenabler()
282 gicd_write_icenabler(base, id, BIT_32(bit_num)); in gicd_set_icenabler()
289 gicd_write_ispendr(base, id, BIT_32(bit_num)); in gicd_set_ispendr()
296 gicd_write_icpendr(base, id, BIT_32(bit_num)); in gicd_set_icpendr()
311 gicd_write_isactiver(base, id, BIT_32(bit_num)); in gicd_set_isactiver()
318 gicd_write_icactiver(base, id, BIT_32(bit_num)); in gicd_set_icactiver()

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