1 /* 2 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP_RIFSC_REGS_H 8 #define STM32MP_RIFSC_REGS_H 9 10 /* RIFSC offset register */ 11 #define _RIFSC_RISC_CR U(0x0) 12 #define _RIFSC_RISC_SECCFGR(id) (U(0x10) + U(0x4) * ((id) / 32)) 13 #define _RIFSC_RISC_PRIVCFGR(id) (U(0x30) + U(0x4) * ((id) / 32)) 14 #define _RIFSC_RISC_RCFGLOCKR(id) (U(0x50) + U(0x4) * ((id) / 32)) 15 #define _RIFSC_RISC_PERy_CIDCFGR(id) (U(0x100) + U(0x8) * (id)) 16 #define _RIFSC_RISC_PERy_SEMCR(id) (U(0x104) + U(0x8) * (id)) 17 #define _RIFSC_RIMC_CR U(0xC00) 18 #define _RIFSC_RIMC_SR U(0xC04) 19 #define _RIFSC_RIMC_ATTR(x) (U(0xC10) + U(0x4) * (x)) 20 #define _RIFSC_PPSR(x) (U(0xFB0) + U(0x4) * (x)) 21 #define _RIFSC_HWCFGR3 U(0xFE8) 22 #define _RIFSC_HWCFGR2 U(0xFEC) 23 #define _RIFSC_HWCFGR1 U(0xFF0) 24 #define _RIFSC_VERR U(0xFF4) 25 #define _RFISC_IPIDR U(0xFF8) 26 #define _RFISC_SIDR U(0xFFC) 27 28 /* RIFSC_RIMC_ATTRx register fields */ 29 #define RIFSC_RIMC_ATTRx_CIDSEL BIT_32(2) 30 #define RIFSC_RIMC_ATTRx_MCID_MASK GENMASK_32(6, 4) 31 #define RIFSC_RIMC_ATTRx_MCID_SHIFT 4 32 #define RIFSC_RIMC_ATTRx_MSEC BIT_32(8) 33 #define RIFSC_RIMC_ATTRx_MPRIV BIT_32(9) 34 35 36 /* RIFSC_RISC_PERy_CIDCFGR register fields */ 37 #define _RIFSC_CIDCFGR_CFEN BIT_32(0) 38 #define _RIFSC_CIDCFGR_SEM_EN BIT_32(1) 39 #define _RIFSC_CIDCFGR_SCID_SHIFT U(4) 40 #define _RIFSC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 41 #define _RIFSC_CIDCFGR_SEML_SHIFT U(16) 42 #define _RIFSC_CIDCFGR_SEML_MASK GENMASK_32(23, 16) 43 44 /* RIFSC_RISC_PERy_SEMCR register fields */ 45 #define _RIFSC_SEMCR_SEM_MUTEX BIT_32(0) 46 #define _RIFSC_SEMCR_SEMCID_SHIFT U(4) 47 #define _RIFSC_SEMCR_SEMCID_MASK GENMASK_32(6, 4) 48 49 #endif /* STM32MP_RIFSC_REGS_H */ 50