1 /* 2 * Copyright (c) 2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_RISAF_H 8 #define STM32MP2_RISAF_H 9 10 #include <stdint.h> 11 12 #include <lib/utils_def.h> 13 14 /* RISAF general registers (base relative) */ 15 #define _RISAF_CR U(0x00) 16 #define _RISAF_SR U(0x04) 17 #define _RISAF_KEYR U(0x30) 18 #define _RISAF_HWCFGR U(0xFF0) 19 20 /* RISAF general register field description */ 21 /* _RISAF_CR register fields */ 22 #define _RISAF_CR_GLOCK BIT_32(0) 23 /* _RISAF_SR register fields */ 24 #define _RISAF_SR_KEYVALID BIT_32(0) 25 #define _RISAF_SR_KEYRDY BIT_32(1) 26 #define _RISAF_SR_ENCDIS BIT_32(2) 27 /* _RISAF_HWCFGR register fields */ 28 #define _RISAF_HWCFGR_CFG1_SHIFT 0 29 #define _RISAF_HWCFGR_CFG1_MASK GENMASK_32(7, 0) 30 #define _RISAF_HWCFGR_CFG2_SHIFT 8 31 #define _RISAF_HWCFGR_CFG2_MASK GENMASK_32(15, 8) 32 #define _RISAF_HWCFGR_CFG3_SHIFT 16 33 #define _RISAF_HWCFGR_CFG3_MASK GENMASK_32(23, 16) 34 #define _RISAF_HWCFGR_CFG4_SHIFT 24 35 #define _RISAF_HWCFGR_CFG4_MASK GENMASK_32(31, 24) 36 37 /* RISAF region registers (base relative) */ 38 #define _RISAF_REG_BASE U(0x40) 39 #define _RISAF_REG_SIZE U(0x40) 40 #define _RISAF_REG(n) (_RISAF_REG_BASE + (((n) - 1) * _RISAF_REG_SIZE)) 41 #define _RISAF_REG_CFGR_OFFSET U(0x0) 42 #define _RISAF_REG_CFGR(n) (_RISAF_REG(n) + _RISAF_REG_CFGR_OFFSET) 43 #define _RISAF_REG_STARTR_OFFSET U(0x4) 44 #define _RISAF_REG_STARTR(n) (_RISAF_REG(n) + _RISAF_REG_STARTR_OFFSET) 45 #define _RISAF_REG_ENDR_OFFSET U(0x8) 46 #define _RISAF_REG_ENDR(n) (_RISAF_REG(n) + _RISAF_REG_ENDR_OFFSET) 47 #define _RISAF_REG_CIDCFGR_OFFSET U(0xC) 48 #define _RISAF_REG_CIDCFGR(n) (_RISAF_REG(n) + _RISAF_REG_CIDCFGR_OFFSET) 49 50 /* RISAF region register field description */ 51 /* _RISAF_REG_CFGR(n) register fields */ 52 #define _RISAF_REG_CFGR_BREN_SHIFT 0 53 #define _RISAF_REG_CFGR_BREN BIT_32(_RISAF_REG_CFGR_BREN_SHIFT) 54 #define _RISAF_REG_CFGR_SEC_SHIFT 8 55 #define _RISAF_REG_CFGR_SEC BIT_32(_RISAF_REG_CFGR_SEC_SHIFT) 56 #define _RISAF_REG_CFGR_ENC_SHIFT 15 57 #define _RISAF_REG_CFGR_ENC BIT_32(_RISAF_REG_CFGR_ENC_SHIFT) 58 #define _RISAF_REG_CFGR_PRIVC_SHIFT 16 59 #define _RISAF_REG_CFGR_PRIVC_MASK GENMASK_32(23, 16) 60 #define _RISAF_REG_CFGR_ALL_MASK (_RISAF_REG_CFGR_BREN | _RISAF_REG_CFGR_SEC | \ 61 _RISAF_REG_CFGR_ENC | _RISAF_REG_CFGR_PRIVC_MASK) 62 /* _RISAF_REG_CIDCFGR(n) register fields */ 63 #define _RISAF_REG_CIDCFGR_RDENC_SHIFT 0 64 #define _RISAF_REG_CIDCFGR_RDENC_MASK GENMASK_32(7, 0) 65 #define _RISAF_REG_CIDCFGR_WRENC_SHIFT 16 66 #define _RISAF_REG_CIDCFGR_WRENC_MASK GENMASK_32(23, 16) 67 #define _RISAF_REG_CIDCFGR_ALL_MASK (_RISAF_REG_CIDCFGR_RDENC_MASK | \ 68 _RISAF_REG_CIDCFGR_WRENC_MASK) 69 70 /* Device Tree related definitions */ 71 #define DT_RISAF_COMPAT "st,stm32-risaf" 72 #define DT_RISAF_REG_ID_MASK U(0xF) 73 #define DT_RISAF_EN_SHIFT 5 74 #define DT_RISAF_EN_MASK BIT_32(DT_RISAF_EN_SHIFT) 75 #define DT_RISAF_SEC_SHIFT 6 76 #define DT_RISAF_SEC_MASK BIT_32(DT_RISAF_SEC_SHIFT) 77 #define DT_RISAF_ENC_SHIFT 7 78 #define DT_RISAF_ENC_MASK BIT_32(DT_RISAF_ENC_SHIFT) 79 #define DT_RISAF_PRIV_SHIFT 8 80 #define DT_RISAF_PRIV_MASK GENMASK_32(15, 8) 81 #define DT_RISAF_READ_SHIFT 16 82 #define DT_RISAF_READ_MASK GENMASK_32(23, 16) 83 #define DT_RISAF_WRITE_SHIFT 24 84 #define DT_RISAF_WRITE_MASK GENMASK_32(31, 24) 85 86 /* RISAF max properties */ 87 #define RISAF_REGION_REG_SIZE (4 * sizeof(uint32_t)) 88 #define RISAF_REGION_PROTREG_SIZE (1 * sizeof(uint32_t)) 89 #define RISAF_TIMEOUT_1MS_IN_US U(1000) 90 91 /* RISAF encryption key size in bytes */ 92 #define RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES U(16) 93 94 struct stm32mp2_risaf_region { 95 int instance; 96 uint32_t cfg; 97 uintptr_t addr; 98 size_t len; 99 }; 100 101 struct stm32mp2_risaf_platdata { 102 uintptr_t *base; 103 unsigned long *clock; 104 uint32_t *granularity; 105 struct stm32mp2_risaf_region *region; 106 int nregions; 107 }; 108 109 int stm32mp2_risaf_write_encryption_key(int instance, uint8_t *key); 110 int stm32mp2_risaf_lock(int instance); 111 int stm32mp2_risaf_is_locked(int instance, bool *state); 112 int stm32mp2_risaf_init(void); 113 114 #endif /* STM32MP2_RISAF_H */ 115