Lines Matching refs:BIT_32
17 #define CPU_PWR_CTL_CLAMP BIT_32(0)
18 #define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1)
19 #define CPU_PWR_CTL_L1_RST_DIS BIT_32(2)
20 #define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3)
21 #define CPU_PWR_CTL_CORE_RST BIT_32(4)
22 #define CPU_PWR_CTL_COREPOR_RST BIT_32(5)
23 #define CPU_PWR_CTL_GATE_CLK BIT_32(6)
24 #define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7)
26 #define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
34 #define PWR_CTL_OVERRIDE_PRESETDBG BIT_32(22)
36 #define L2_PWR_CTL_L2_ARRAY_HS BIT_32(0)
37 #define L2_PWR_CTL_SCU_ARRAY_HS BIT_32(1)
38 #define L2_PWR_CTL_L2_RST_DIS BIT_32(2)
39 #define L2_PWR_CTL_L2_HS_CLAMP BIT_32(8)
40 #define L2_PWR_CTL_L2_HS_EN BIT_32(9)
41 #define L2_PWR_CTL_L2_HS_RST BIT_32(10)
42 #define L2_PWR_CTL_L2_SLEEP_STATE BIT_32(11)
43 #define L2_PWR_CTL_SYS_RESET BIT_32(12)
44 #define L2_PWR_CTL_L2_RET_SLP BIT_32(13)
45 #define L2_PWR_CTL_SCU_ARRAY_HS_CLAMP BIT_32(14)
46 #define L2_PWR_CTL_L2_ARRAY_HS_CLAMP BIT_32(15)
48 #define L2_PWR_CTL_PMIC_APC_ON BIT_32(28)
50 #define L2_PWR_STATUS_L2_HS_STS BIT_32(9)
52 #define CORE_CBCR_CLK_ENABLE BIT_32(0)
53 #define CORE_CBCR_HW_CTL BIT_32(1)