1*8934c7b0SMaxime Méré /* 2*8934c7b0SMaxime Méré * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 3*8934c7b0SMaxime Méré * 4*8934c7b0SMaxime Méré * SPDX-License-Identifier: BSD-3-Clause 5*8934c7b0SMaxime Méré */ 6*8934c7b0SMaxime Méré 7*8934c7b0SMaxime Méré #ifndef STM32MP_RIFSC_REGS_H 8*8934c7b0SMaxime Méré #define STM32MP_RIFSC_REGS_H 9*8934c7b0SMaxime Méré 10*8934c7b0SMaxime Méré /* RIFSC offset register */ 11*8934c7b0SMaxime Méré #define _RIFSC_RISC_CR U(0x0) 12*8934c7b0SMaxime Méré #define _RIFSC_RISC_SECCFGR(id) (U(0x10) + U(0x4) * ((id) / 32)) 13*8934c7b0SMaxime Méré #define _RIFSC_RISC_PRIVCFGR(id) (U(0x30) + U(0x4) * ((id) / 32)) 14*8934c7b0SMaxime Méré #define _RIFSC_RISC_RCFGLOCKR(id) (U(0x50) + U(0x4) * ((id) / 32)) 15*8934c7b0SMaxime Méré #define _RIFSC_RISC_PERy_CIDCFGR(id) (U(0x100) + U(0x8) * (id)) 16*8934c7b0SMaxime Méré #define _RIFSC_RISC_PERy_SEMCR(id) (U(0x104) + U(0x8) * (id)) 17*8934c7b0SMaxime Méré #define _RIFSC_RIMC_CR U(0xC00) 18*8934c7b0SMaxime Méré #define _RIFSC_RIMC_SR U(0xC04) 19*8934c7b0SMaxime Méré #define _RIFSC_RIMC_ATTR(x) (U(0xC10) + U(0x4) * (x)) 20*8934c7b0SMaxime Méré #define _RIFSC_PPSR(x) (U(0xFB0) + U(0x4) * (x)) 21*8934c7b0SMaxime Méré #define _RIFSC_HWCFGR3 U(0xFE8) 22*8934c7b0SMaxime Méré #define _RIFSC_HWCFGR2 U(0xFEC) 23*8934c7b0SMaxime Méré #define _RIFSC_HWCFGR1 U(0xFF0) 24*8934c7b0SMaxime Méré #define _RIFSC_VERR U(0xFF4) 25*8934c7b0SMaxime Méré #define _RFISC_IPIDR U(0xFF8) 26*8934c7b0SMaxime Méré #define _RFISC_SIDR U(0xFFC) 27*8934c7b0SMaxime Méré 28*8934c7b0SMaxime Méré /* RIFSC_RIMC_ATTRx register fields */ 29*8934c7b0SMaxime Méré #define RIFSC_RIMC_ATTRx_CIDSEL BIT_32(2) 30*8934c7b0SMaxime Méré #define RIFSC_RIMC_ATTRx_MCID_MASK GENMASK_32(6, 4) 31*8934c7b0SMaxime Méré #define RIFSC_RIMC_ATTRx_MCID_SHIFT 4 32*8934c7b0SMaxime Méré #define RIFSC_RIMC_ATTRx_MSEC BIT_32(8) 33*8934c7b0SMaxime Méré #define RIFSC_RIMC_ATTRx_MPRIV BIT_32(9) 34*8934c7b0SMaxime Méré 35*8934c7b0SMaxime Méré 36*8934c7b0SMaxime Méré /* RIFSC_RISC_PERy_CIDCFGR register fields */ 37*8934c7b0SMaxime Méré #define _RIFSC_CIDCFGR_CFEN BIT_32(0) 38*8934c7b0SMaxime Méré #define _RIFSC_CIDCFGR_SEM_EN BIT_32(1) 39*8934c7b0SMaxime Méré #define _RIFSC_CIDCFGR_SCID_SHIFT U(4) 40*8934c7b0SMaxime Méré #define _RIFSC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 41*8934c7b0SMaxime Méré #define _RIFSC_CIDCFGR_SEML_SHIFT U(16) 42*8934c7b0SMaxime Méré #define _RIFSC_CIDCFGR_SEML_MASK GENMASK_32(23, 16) 43*8934c7b0SMaxime Méré 44*8934c7b0SMaxime Méré /* RIFSC_RISC_PERy_SEMCR register fields */ 45*8934c7b0SMaxime Méré #define _RIFSC_SEMCR_SEM_MUTEX BIT_32(0) 46*8934c7b0SMaxime Méré #define _RIFSC_SEMCR_SEMCID_SHIFT U(4) 47*8934c7b0SMaxime Méré #define _RIFSC_SEMCR_SEMCID_MASK GENMASK_32(6, 4) 48*8934c7b0SMaxime Méré 49*8934c7b0SMaxime Méré #endif /* STM32MP_RIFSC_REGS_H */ 50