| #
e4731b1c |
| 23-Jan-2026 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "upstream_ddr_training" into integration
* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add
Merge changes from topic "upstream_ddr_training" into integration
* changes:
feat(s32g274ardb): add DDR post training setup
feat(s32g274ardb): add training for 1D and 2D
feat(s32g274ardb): add DDR training stubs
show more ...
|
| #
a60aeae7 |
| 09-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR post training setup
Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.
The post training setup is now
feat(s32g274ardb): add DDR post training setup
Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.
The post training setup is now integrated into
the DDR initialization flow.
Change-Id: I457d1f58479b282607c9d42773d6f922f563b2fb
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
show more ...
|
| #
47f0a591 |
| 09-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add training for 1D and 2D
Extend the logic for executing the training stage
to include 1D and 2D PHY training.
Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by
feat(s32g274ardb): add training for 1D and 2D
Extend the logic for executing the training stage
to include 1D and 2D PHY training.
Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
show more ...
|
| #
2147ce91 |
| 19-Jan-2026 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "upstream_ddr_reg_accesories" into integration
* changes:
feat(s32g274ardb): add DDR register accessories
feat(s32g274ardb): add DDR PHY mailbox support
|
| #
a4efd428 |
| 01-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR register accessories
Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.
These
feat(s32g274ardb): add DDR register accessories
Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.
These utilities encapsulate register access
patterns and are used for delay calibration,
Vref averaging, memory type detection and PLL
source selection.
Change-Id: I5415a650f6430578a8cca13ff7e144b471c61466
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
show more ...
|
| #
30c8a20d |
| 01-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR PHY mailbox support
Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution s
feat(s32g274ardb): add DDR PHY mailbox support
Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution status monitoring.
This enables reliable tracking of firmware
progress during DDR initialization and training,
Change-Id: I4fdd582fcc9a88c09c820ce9e59fe14ec3c043a8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
show more ...
|