Lines Matching refs:BIT_32
72 #define PWR_CR1_VDDIO3VMEN BIT_32(0)
73 #define PWR_CR1_VDDIO4VMEN BIT_32(1)
74 #define PWR_CR1_USB33VMEN BIT_32(2)
75 #define PWR_CR1_UCPDVMEN BIT_32(3)
76 #define PWR_CR1_AVMEN BIT_32(4)
77 #define PWR_CR1_VDDIO3SV BIT_32(8)
78 #define PWR_CR1_VDDIO4SV BIT_32(9)
79 #define PWR_CR1_USB33SV BIT_32(10)
80 #define PWR_CR1_UCPDSV BIT_32(11)
81 #define PWR_CR1_ASV BIT_32(12)
82 #define PWR_CR1_VDDIO3RDY BIT_32(16)
83 #define PWR_CR1_VDDIO4RDY BIT_32(17)
84 #define PWR_CR1_USB33RDY BIT_32(18)
85 #define PWR_CR1_UCPDRDY BIT_32(19)
86 #define PWR_CR1_ARDY BIT_32(20)
87 #define PWR_CR1_VDDIOVRSEL BIT_32(24)
88 #define PWR_CR1_VDDIO3VRSEL BIT_32(25)
89 #define PWR_CR1_VDDIO4VRSEL BIT_32(26)
90 #define PWR_CR1_GPVMO BIT_32(31)
93 #define PWR_CR2_MONEN BIT_32(0)
94 #define PWR_CR2_VBATL BIT_32(8)
95 #define PWR_CR2_VBATH BIT_32(9)
96 #define PWR_CR2_TEMPL BIT_32(10)
97 #define PWR_CR2_TEMPH BIT_32(11)
100 #define PWR_CR3_PVDEN BIT_32(0)
101 #define PWR_CR3_PVDO BIT_32(8)
104 #define PWR_CR5_VCOREMONEN BIT_32(0)
105 #define PWR_CR5_VCOREL BIT_32(8)
106 #define PWR_CR5_VCOREH BIT_32(9)
109 #define PWR_CR6_VCPUMONEN BIT_32(0)
110 #define PWR_CR6_VCPULLS BIT_32(4)
111 #define PWR_CR6_VCPUL BIT_32(8)
112 #define PWR_CR6_VCPUH BIT_32(9)
115 #define PWR_CR7_VDDIO2VMEN BIT_32(0)
116 #define PWR_CR7_VDDIO2SV BIT_32(8)
117 #define PWR_CR7_VDDIO2RDY BIT_32(16)
118 #define PWR_CR7_VDDIO2VRSEL BIT_32(24)
119 #define PWR_CR7_VDDIO2VRSTBY BIT_32(25)
122 #define PWR_CR8_VDDIO1VMEN BIT_32(0)
123 #define PWR_CR8_VDDIO1SV BIT_32(8)
124 #define PWR_CR8_VDDIO1RDY BIT_32(16)
125 #define PWR_CR8_VDDIO1VRSEL BIT_32(24)
126 #define PWR_CR8_VDDIO1VRSTBY BIT_32(25)
129 #define PWR_CR9_BKPRBSEN BIT_32(0)
130 #define PWR_CR9_LPR1BSEN BIT_32(4)
137 #define PWR_CR11_DDRRETDIS BIT_32(0)
140 #define PWR_CR12_GPUVMEN BIT_32(0)
141 #define PWR_CR12_GPULVTEN BIT_32(1)
142 #define PWR_CR12_GPUSV BIT_32(8)
143 #define PWR_CR12_VDDGPURDY BIT_32(16)
146 #define PWR_UCPDR_UCPD_DBDIS BIT_32(0)
147 #define PWR_UCPDR_UCPD_STBY BIT_32(1)
150 #define PWR_BDCR1_DBD3P BIT_32(0)
153 #define PWR_BDCR2_DBP BIT_32(0)
156 #define PWR_CPU1CR_PDDS_D2 BIT_32(0)
157 #define PWR_CPU1CR_PDDS_D1 BIT_32(1)
158 #define PWR_CPU1CR_VBF BIT_32(4)
159 #define PWR_CPU1CR_STOPF BIT_32(5)
160 #define PWR_CPU1CR_SBF BIT_32(6)
161 #define PWR_CPU1CR_SBF_D1 BIT_32(7)
162 #define PWR_CPU1CR_SBF_D3 BIT_32(8)
163 #define PWR_CPU1CR_CSSF BIT_32(9)
164 #define PWR_CPU1CR_STANDBYWFIL2 BIT_32(15)
165 #define PWR_CPU1CR_LPDS_D1 BIT_32(16)
166 #define PWR_CPU1CR_LVDS_D1 BIT_32(17)
169 #define PWR_CPU2CR_PDDS_D2 BIT_32(0)
170 #define PWR_CPU2CR_VBF BIT_32(4)
171 #define PWR_CPU2CR_STOPF BIT_32(5)
172 #define PWR_CPU2CR_SBF BIT_32(6)
173 #define PWR_CPU2CR_SBF_D2 BIT_32(7)
174 #define PWR_CPU2CR_SBF_D3 BIT_32(8)
175 #define PWR_CPU2CR_CSSF BIT_32(9)
176 #define PWR_CPU2CR_DEEPSLEEP BIT_32(15)
177 #define PWR_CPU2CR_LPDS_D2 BIT_32(16)
178 #define PWR_CPU2CR_LVDS_D2 BIT_32(17)
181 #define PWR_CPU3CR_VBF BIT_32(4)
182 #define PWR_CPU3CR_SBF_D3 BIT_32(8)
183 #define PWR_CPU3CR_CSSF BIT_32(9)
184 #define PWR_CPU3CR_DEEPSLEEP BIT_32(15)
187 #define PWR_D1CR_LPCFG_D1 BIT_32(0)
192 #define PWR_D2CR_LPCFG_D2 BIT_32(0)
201 #define PWR_D3CR_PDDS_D3 BIT_32(0)
202 #define PWR_D3CR_D3RDY BIT_32(31)
205 #define PWR_WKUPCR1_WKUPC BIT_32(0)
206 #define PWR_WKUPCR1_WKUPP BIT_32(8)
209 #define PWR_WKUPCR1_WKUPENCPU1 BIT_32(16)
210 #define PWR_WKUPCR1_WKUPENCPU2 BIT_32(17)
211 #define PWR_WKUPCR1_WKUPF BIT_32(31)
214 #define PWR_WKUPCR2_WKUPC BIT_32(0)
215 #define PWR_WKUPCR2_WKUPP BIT_32(8)
218 #define PWR_WKUPCR2_WKUPENCPU1 BIT_32(16)
219 #define PWR_WKUPCR2_WKUPENCPU2 BIT_32(17)
220 #define PWR_WKUPCR2_WKUPF BIT_32(31)
223 #define PWR_WKUPCR3_WKUPC BIT_32(0)
224 #define PWR_WKUPCR3_WKUPP BIT_32(8)
227 #define PWR_WKUPCR3_WKUPENCPU1 BIT_32(16)
228 #define PWR_WKUPCR3_WKUPENCPU2 BIT_32(17)
229 #define PWR_WKUPCR3_WKUPF BIT_32(31)
232 #define PWR_WKUPCR4_WKUPC BIT_32(0)
233 #define PWR_WKUPCR4_WKUPP BIT_32(8)
236 #define PWR_WKUPCR4_WKUPENCPU1 BIT_32(16)
237 #define PWR_WKUPCR4_WKUPENCPU2 BIT_32(17)
238 #define PWR_WKUPCR4_WKUPF BIT_32(31)
241 #define PWR_WKUPCR5_WKUPC BIT_32(0)
242 #define PWR_WKUPCR5_WKUPP BIT_32(8)
245 #define PWR_WKUPCR5_WKUPENCPU1 BIT_32(16)
246 #define PWR_WKUPCR5_WKUPENCPU2 BIT_32(17)
247 #define PWR_WKUPCR5_WKUPF BIT_32(31)
250 #define PWR_WKUPCR6_WKUPC BIT_32(0)
251 #define PWR_WKUPCR6_WKUPP BIT_32(8)
254 #define PWR_WKUPCR6_WKUPENCPU1 BIT_32(16)
255 #define PWR_WKUPCR6_WKUPENCPU2 BIT_32(17)
256 #define PWR_WKUPCR6_WKUPF BIT_32(31)
259 #define PWR_D3WKUPENR_TAMP_WKUPEN_D3 BIT_32(0)
262 #define PWR_RSECCFGR_RSEC0 BIT_32(0)
263 #define PWR_RSECCFGR_RSEC1 BIT_32(1)
264 #define PWR_RSECCFGR_RSEC2 BIT_32(2)
265 #define PWR_RSECCFGR_RSEC3 BIT_32(3)
266 #define PWR_RSECCFGR_RSEC4 BIT_32(4)
267 #define PWR_RSECCFGR_RSEC5 BIT_32(5)
268 #define PWR_RSECCFGR_RSEC6 BIT_32(6)
271 #define PWR_RPRIVCFGR_RPRIV0 BIT_32(0)
272 #define PWR_RPRIVCFGR_RPRIV1 BIT_32(1)
273 #define PWR_RPRIVCFGR_RPRIV2 BIT_32(2)
274 #define PWR_RPRIVCFGR_RPRIV3 BIT_32(3)
275 #define PWR_RPRIVCFGR_RPRIV4 BIT_32(4)
276 #define PWR_RPRIVCFGR_RPRIV5 BIT_32(5)
277 #define PWR_RPRIVCFGR_RPRIV6 BIT_32(6)
280 #define PWR_R0CIDCFGR_CFEN BIT_32(0)
285 #define PWR_R1CIDCFGR_CFEN BIT_32(0)
290 #define PWR_R2CIDCFGR_CFEN BIT_32(0)
295 #define PWR_R3CIDCFGR_CFEN BIT_32(0)
300 #define PWR_R4CIDCFGR_CFEN BIT_32(0)
305 #define PWR_R5CIDCFGR_CFEN BIT_32(0)
310 #define PWR_R6CIDCFGR_CFEN BIT_32(0)
315 #define PWR_WIOSECCFGR_WIOSEC1 BIT_32(0)
316 #define PWR_WIOSECCFGR_WIOSEC2 BIT_32(1)
317 #define PWR_WIOSECCFGR_WIOSEC3 BIT_32(2)
318 #define PWR_WIOSECCFGR_WIOSEC4 BIT_32(3)
319 #define PWR_WIOSECCFGR_WIOSEC5 BIT_32(4)
320 #define PWR_WIOSECCFGR_WIOSEC6 BIT_32(5)
323 #define PWR_WIOPRIVCFGR_WIOPRIV1 BIT_32(0)
324 #define PWR_WIOPRIVCFGR_WIOPRIV2 BIT_32(1)
325 #define PWR_WIOPRIVCFGR_WIOPRIV3 BIT_32(2)
326 #define PWR_WIOPRIVCFGR_WIOPRIV4 BIT_32(3)
327 #define PWR_WIOPRIVCFGR_WIOPRIV5 BIT_32(4)
328 #define PWR_WIOPRIVCFGR_WIOPRIV6 BIT_32(5)
331 #define PWR_WIO1CIDCFGR_CFEN BIT_32(0)
332 #define PWR_WIO1CIDCFGR_SEM_EN BIT_32(1)
335 #define PWR_WIO1CIDCFGR_SEMWLC0 BIT_32(16)
336 #define PWR_WIO1CIDCFGR_SEMWLC1 BIT_32(17)
337 #define PWR_WIO1CIDCFGR_SEMWLC2 BIT_32(18)
338 #define PWR_WIO1CIDCFGR_SEMWLC3 BIT_32(19)
339 #define PWR_WIO1CIDCFGR_SEMWLC4 BIT_32(20)
340 #define PWR_WIO1CIDCFGR_SEMWLC5 BIT_32(21)
341 #define PWR_WIO1CIDCFGR_SEMWLC6 BIT_32(22)
342 #define PWR_WIO1CIDCFGR_SEMWLC7 BIT_32(23)
345 #define PWR_WIO1SEMCR_SEM_MUTEX BIT_32(0)
350 #define PWR_WIO2CIDCFGR_CFEN BIT_32(0)
351 #define PWR_WIO2CIDCFGR_SEM_EN BIT_32(1)
354 #define PWR_WIO2CIDCFGR_SEMWLC0 BIT_32(16)
355 #define PWR_WIO2CIDCFGR_SEMWLC1 BIT_32(17)
356 #define PWR_WIO2CIDCFGR_SEMWLC2 BIT_32(18)
357 #define PWR_WIO2CIDCFGR_SEMWLC3 BIT_32(19)
358 #define PWR_WIO2CIDCFGR_SEMWLC4 BIT_32(20)
359 #define PWR_WIO2CIDCFGR_SEMWLC5 BIT_32(21)
360 #define PWR_WIO2CIDCFGR_SEMWLC6 BIT_32(22)
361 #define PWR_WIO2CIDCFGR_SEMWLC7 BIT_32(23)
364 #define PWR_WIO2SEMCR_SEM_MUTEX BIT_32(0)
369 #define PWR_WIO3CIDCFGR_CFEN BIT_32(0)
370 #define PWR_WIO3CIDCFGR_SEM_EN BIT_32(1)
373 #define PWR_WIO3CIDCFGR_SEMWLC0 BIT_32(16)
374 #define PWR_WIO3CIDCFGR_SEMWLC1 BIT_32(17)
375 #define PWR_WIO3CIDCFGR_SEMWLC2 BIT_32(18)
376 #define PWR_WIO3CIDCFGR_SEMWLC3 BIT_32(19)
377 #define PWR_WIO3CIDCFGR_SEMWLC4 BIT_32(20)
378 #define PWR_WIO3CIDCFGR_SEMWLC5 BIT_32(21)
379 #define PWR_WIO3CIDCFGR_SEMWLC6 BIT_32(22)
380 #define PWR_WIO3CIDCFGR_SEMWLC7 BIT_32(23)
383 #define PWR_WIO3SEMCR_SEM_MUTEX BIT_32(0)
388 #define PWR_WIO4CIDCFGR_CFEN BIT_32(0)
389 #define PWR_WIO4CIDCFGR_SEM_EN BIT_32(1)
392 #define PWR_WIO4CIDCFGR_SEMWLC0 BIT_32(16)
393 #define PWR_WIO4CIDCFGR_SEMWLC1 BIT_32(17)
394 #define PWR_WIO4CIDCFGR_SEMWLC2 BIT_32(18)
395 #define PWR_WIO4CIDCFGR_SEMWLC3 BIT_32(19)
396 #define PWR_WIO4CIDCFGR_SEMWLC4 BIT_32(20)
397 #define PWR_WIO4CIDCFGR_SEMWLC5 BIT_32(21)
398 #define PWR_WIO4CIDCFGR_SEMWLC6 BIT_32(22)
399 #define PWR_WIO4CIDCFGR_SEMWLC7 BIT_32(23)
402 #define PWR_WIO4SEMCR_SEM_MUTEX BIT_32(0)
407 #define PWR_WIO5CIDCFGR_CFEN BIT_32(0)
408 #define PWR_WIO5CIDCFGR_SEM_EN BIT_32(1)
411 #define PWR_WIO5CIDCFGR_SEMWLC0 BIT_32(16)
412 #define PWR_WIO5CIDCFGR_SEMWLC1 BIT_32(17)
413 #define PWR_WIO5CIDCFGR_SEMWLC2 BIT_32(18)
414 #define PWR_WIO5CIDCFGR_SEMWLC3 BIT_32(19)
415 #define PWR_WIO5CIDCFGR_SEMWLC4 BIT_32(20)
416 #define PWR_WIO5CIDCFGR_SEMWLC5 BIT_32(21)
417 #define PWR_WIO5CIDCFGR_SEMWLC6 BIT_32(22)
418 #define PWR_WIO5CIDCFGR_SEMWLC7 BIT_32(23)
421 #define PWR_WIO5SEMCR_SEM_MUTEX BIT_32(0)
426 #define PWR_WIO6CIDCFGR_CFEN BIT_32(0)
427 #define PWR_WIO6CIDCFGR_SEM_EN BIT_32(1)
430 #define PWR_WIO6CIDCFGR_SEMWLC0 BIT_32(16)
431 #define PWR_WIO6CIDCFGR_SEMWLC1 BIT_32(17)
432 #define PWR_WIO6CIDCFGR_SEMWLC2 BIT_32(18)
433 #define PWR_WIO6CIDCFGR_SEMWLC3 BIT_32(19)
434 #define PWR_WIO6CIDCFGR_SEMWLC4 BIT_32(20)
435 #define PWR_WIO6CIDCFGR_SEMWLC5 BIT_32(21)
436 #define PWR_WIO6CIDCFGR_SEMWLC6 BIT_32(22)
437 #define PWR_WIO6CIDCFGR_SEMWLC7 BIT_32(23)
440 #define PWR_WIO6SEMCR_SEM_MUTEX BIT_32(0)
445 #define PWR_CPU1D1SR_HOLD_BOOT BIT_32(0)
452 #define PWR_CPU2D2SR_HOLD_BOOT BIT_32(0)
453 #define PWR_CPU2D2SR_WFBEN BIT_32(1)
466 #define PWR_DBGR_FD3S BIT_32(0)
467 #define PWR_DBGR_VDDIOKRETRAM BIT_32(16)
468 #define PWR_DBGR_VDDIOKBKPRAM BIT_32(17)
469 #define PWR_DBGR_VDDIOKD3 BIT_32(18)
470 #define PWR_DBGR_VDDIOKLPSRAM1 BIT_32(19)