| #
d1b5ada8 |
| 19-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "msm8916-plats" into integration
* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms
Merge changes from topic "msm8916-plats" into integration
* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms
feat(msm8916): add port for MSM8939
feat(msm8916): power on L2 caches for secondary clusters
feat(msm8916): initialize CCI-400 for multiple clusters
refactor(msm8916): handle multiple CPU clusters
feat(msm8916): add port for MSM8909
feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+
style(msm8916): add missing braces to while statements
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|
| #
c822d265 |
| 16-Sep-2022 |
Stephan Gerhold <stephan@gerhold.net> |
feat(msm8916): power on L2 caches for secondary clusters
On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it
feat(msm8916): power on L2 caches for secondary clusters
On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it
up for secondary clusters similar to the CPU boot sequence.
No functional change for platforms with a single cluster. The new code
is discarded entirely in this case.
Change-Id: I3d3bce519a8a10ef5278d74d81acf59123e00454
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
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|
| #
1d7ed58f |
| 16-Sep-2022 |
Stephan Gerhold <stephan@gerhold.net> |
refactor(msm8916): handle multiple CPU clusters
Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured
refactor(msm8916): handle multiple CPU clusters
Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured separately.
Refactor the code to handle additional clusters by introducing loops
and some conditionals.
No functional change for existing single cluster platforms.
Change-Id: I5b4b1ad2a1adde559d5b79b7698afe73733b2e90
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
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| #
e0a6a512 |
| 03-Feb-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "msm8916" into integration
* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding G
Merge changes from topic "msm8916" into integration
* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding GICD_PIDR2_GICV2 address
feat(msm8916): initial platform port
docs(msm8916): new port for Qualcomm Snapdragon 410
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| #
a758c0b6 |
| 01-Dec-2021 |
Stephan Gerhold <stephan@gerhold.net> |
feat(msm8916): allow booting secondary CPU cores
Add support for the PSCI CPU_ON call to allow booting secondary CPU
cores. On cold boot they need to be booted with a special register
sequence. Also
feat(msm8916): allow booting secondary CPU cores
Add support for the PSCI CPU_ON call to allow booting secondary CPU
cores. On cold boot they need to be booted with a special register
sequence. Also, the "boot remapper" needs to be configured to point to
the BL31_BASE, so the CPUs actually start executing BL31 after reset.
Change-Id: I406c508070ccb046bfdefd51554f12e1db671fd4
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
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