| #
8babf73f |
| 14-Apr-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_versal2_ipi" into integration
* changes:
feat(versal2): add bufferless IPI Support
chore(versal2): use BIT_32() macro
|
| #
af22b19d |
| 07-Apr-2025 |
Ben Levinsky <ben.levinsky@amd.com> |
feat(versal2): add bufferless IPI Support
Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.
Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.
Change-Id: I1dc11c8473c390a517fdd3a9
feat(versal2): add bufferless IPI Support
Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.
Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.
Change-Id: I1dc11c8473c390a517fdd3a9e4fc35dc5563792b
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
show more ...
|
| #
e18e67fc |
| 08-Apr-2025 |
Ben Levinsky <ben.levinsky@amd.com> |
chore(versal2): use BIT_32() macro
Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.
Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levin
chore(versal2): use BIT_32() macro
Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.
Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
show more ...
|
| #
6f05b8d4 |
| 18-Jun-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration
|
| #
c97857db |
| 05-Jun-2024 |
Amit Nagal <amit.nagal@amd.com> |
feat(versal2): add support for AMD Versal Gen 2 platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
feat(versal2): add support for AMD Versal Gen 2 platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|