1 /* 2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal Gen 2 IPI management enums and defines */ 9 10 #ifndef PLAT_IPI_H 11 #define PLAT_IPI_H 12 13 #include <stdint.h> 14 #include <lib/utils_def.h> 15 16 #include <ipi.h> 17 18 /********************************************************************* 19 * IPI agent IDs macros 20 ********************************************************************/ 21 #define IPI_ID_PMC 1U 22 #define IPI_ID_APU 2U 23 #define IPI_ID_RPU0 3U 24 #define IPI_ID_RPU1 4U 25 #define IPI_ID_3 5U 26 #define IPI_ID_4 6U 27 #define IPI_ID_5 7U 28 #define IPI_ID_PMC_NOBUF 8U 29 #define IPI_ID_6_NOBUF_95 9U 30 #define IPI_ID_1_NOBUF 10U 31 #define IPI_ID_2_NOBUF 11U 32 #define IPI_ID_3_NOBUF 12U 33 #define IPI_ID_4_NOBUF 13U 34 #define IPI_ID_5_NOBUF 14U 35 #define IPI_ID_6_NOBUF_101 15U 36 #define IPI_ID_MAX 16U 37 38 /********************************************************************* 39 * IPI message buffers 40 ********************************************************************/ 41 #define IPI_BUFFER_BASEADDR (0xEB3F0000U) 42 43 #define IPI_LOCAL_ID IPI_ID_APU 44 #define IPI_REMOTE_ID IPI_ID_PMC 45 46 #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U)) 47 #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U)) 48 49 #define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U) 50 #define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U) 51 52 #define IPI_BUFFER_MAX_WORDS 8 53 54 #define IPI_BUFFER_REQ_OFFSET 0x0U 55 #define IPI_BUFFER_RESP_OFFSET 0x20U 56 57 /********************************************************************* 58 * Platform specific IPI API declarations 59 ********************************************************************/ 60 61 /* Configure IPI table */ 62 extern void soc_ipi_config_table_init(void); 63 64 /******************************************************************************* 65 * IPI registers and bitfields 66 ******************************************************************************/ 67 #define IPI0_REG_BASE (0xEB330000U) 68 #define IPI0_TRIG_BIT BIT_32(2) 69 #define PMC_IPI_TRIG_BIT BIT_32(1) 70 #define IPI1_REG_BASE (0xEB340000U) 71 #define IPI1_TRIG_BIT BIT_32(3) 72 #define IPI2_REG_BASE (0xEB350000U) 73 #define IPI2_TRIG_BIT BIT_32(4) 74 #define IPI3_REG_BASE (0xEB360000U) 75 #define IPI3_TRIG_BIT BIT_32(5) 76 #define IPI4_REG_BASE (0xEB370000U) 77 #define IPI4_TRIG_BIT BIT_32(6) 78 #define IPI5_REG_BASE (0xEB380000U) 79 #define IPI5_TRIG_BIT BIT_32(7) 80 81 #define PMC_NOBUF_REG_BASE (0xEB390000U) 82 #define PMC_NOBUF_TRIG_BIT BIT_32(8) 83 #define IPI6_NOBUF_95_REG_BASE (0xEB3A0000U) 84 #define IPI6_NOBUF_95_TRIG_BIT BIT_32(9) 85 #define IPI1_NOBUF_REG_BASE (0xEB3B0000U) 86 #define IPI1_NOBUF_TRIG_BIT BIT_32(10) 87 #define IPI2_NOBUF_REG_BASE (0xEB3B1000U) 88 #define IPI2_NOBUF_TRIG_BIT BIT_32(11) 89 #define IPI3_NOBUF_REG_BASE (0xEB3B2000U) 90 #define IPI3_NOBUF_TRIG_BIT BIT_32(12) 91 #define IPI4_NOBUF_REG_BASE (0xEB3B3000U) 92 #define IPI4_NOBUF_TRIG_BIT BIT_32(13) 93 #define IPI5_NOBUF_REG_BASE (0xEB3B4000U) 94 #define IPI5_NOBUF_TRIG_BIT BIT_32(14) 95 #define IPI6_NOBUF_101_REG_BASE (0xEB3B5000U) 96 #define IPI6_NOBUF_101_TRIG_BIT BIT_32(15) 97 98 #endif /* PLAT_IPI_H */ 99