Lines Matching refs:BIT_32
81 #define _DWC3_GSBUSCFG0_INCRBRSTENA BIT_32(0)
82 #define _DWC3_GSBUSCFG0_INCR4BRSTENA BIT_32(1)
83 #define _DWC3_GSBUSCFG0_INCR8BRSTENA BIT_32(2)
84 #define _DWC3_GSBUSCFG0_INCR16BRSTENA BIT_32(3)
85 #define _DWC3_GSBUSCFG0_INCR32BRSTENA BIT_32(4)
86 #define _DWC3_GSBUSCFG0_INCR64BRSTENA BIT_32(5)
87 #define _DWC3_GSBUSCFG0_INCR128BRSTENA BIT_32(6)
88 #define _DWC3_GSBUSCFG0_INCR256BRSTENA BIT_32(7)
89 #define _DWC3_GSBUSCFG0_DESBIGEND BIT_32(10)
90 #define _DWC3_GSBUSCFG0_DATBIGEND BIT_32(11)
103 #define _DWC3_GSBUSCFG1_EN1KPAGE BIT_32(12)
110 #define _DWC3_GTXTHRCFG_USBTXPKTCNTSEL BIT_32(29)
119 #define _DWC3_GRXTHRCFG_USBRXPKTCNTSEL BIT_32(29)
122 #define _DWC3_GCTL_DSBLCLKGTNG BIT_32(0)
123 #define _DWC3_GCTL_GBLHIBERNATIONEN BIT_32(1)
124 #define _DWC3_GCTL_U2EXIT_LFPS BIT_32(2)
125 #define _DWC3_GCTL_DISSCRAMBLE BIT_32(3)
130 #define _DWC3_GCTL_DEBUGATTACH BIT_32(8)
131 #define _DWC3_GCTL_U1U2TIMERSCALE BIT_32(9)
132 #define _DWC3_GCTL_SOFITPSYNC BIT_32(10)
133 #define _DWC3_GCTL_CORESOFTRESET BIT_32(11)
138 #define _DWC3_GCTL_U2RSTECN BIT_32(16)
139 #define _DWC3_GCTL_BYPSSETADDR BIT_32(17)
140 #define _DWC3_GCTL_MASTERFILTBYPASS BIT_32(18)
155 #define _DWC3_GSTS_BUSERRADDRVLD BIT_32(4)
156 #define _DWC3_GSTS_CSRTIMEOUT BIT_32(5)
157 #define _DWC3_GSTS_DEVICE_IP BIT_32(6)
158 #define _DWC3_GSTS_HOST_IP BIT_32(7)
159 #define _DWC3_GSTS_ADP_IP BIT_32(8)
160 #define _DWC3_GSTS_BC_IP BIT_32(9)
161 #define _DWC3_GSTS_OTG_IP BIT_32(10)
162 #define _DWC3_GSTS_SSIC_IP BIT_32(11)
167 #define _DWC3_GUCTL1_LOA_FILTER_EN BIT_32(0)
168 #define _DWC3_GUCTL1_OVRLD_L1_SUSP_COM BIT_32(1)
169 #define _DWC3_GUCTL1_HC_PARCHK_DISABLE BIT_32(2)
170 #define _DWC3_GUCTL1_HC_ERRATA_ENABLE BIT_32(3)
173 #define _DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST BIT_32(8)
174 #define _DWC3_GUCTL1_DEV_HS_NYET_BULK_SPR BIT_32(9)
175 #define _DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT_32(10)
176 #define _DWC3_GUCTL1_PARKMODE_DISABLE_FSLS BIT_32(15)
177 #define _DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT_32(16)
178 #define _DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT_32(17)
179 #define _DWC3_GUCTL1_NAK_PER_ENH_HS BIT_32(18)
180 #define _DWC3_GUCTL1_NAK_PER_ENH_FS BIT_32(19)
181 #define _DWC3_GUCTL1_DEV_LSP_TAIL_LOCK_DIS BIT_32(20)
184 #define _DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT_32(24)
185 #define _DWC3_GUCTL1_P3_IN_U2 BIT_32(25)
186 #define _DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT_32(26)
187 #define _DWC3_GUCTL1_DEV_TRB_OUT_SPR_IND BIT_32(27)
188 #define _DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT_32(28)
189 #define _DWC3_GUCTL1_FILTER_SE0_FSLS_EOP BIT_32(29)
190 #define _DWC3_GUCTL1_DS_RXDET_MAX_TOUT_CTRL BIT_32(30)
191 #define _DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT_32(31)
204 #define _DWC3_GUCTL_INSRTEXTRFSBODI BIT_32(11)
205 #define _DWC3_GUCTL_EXTCAPSUPPTEN BIT_32(12)
206 #define _DWC3_GUCTL_ENOVERLAPCHK BIT_32(13)
207 #define _DWC3_GUCTL_USBHSTINAUTORETRYEN BIT_32(14)
208 #define _DWC3_GUCTL_RESBWHSEPS BIT_32(16)
209 #define _DWC3_GUCTL_SPRSCTRLTRANSEN BIT_32(17)
210 #define _DWC3_GUCTL_NOEXTRDL BIT_32(21)
277 #define _DWC3_GHWPARAMS1_GHWPARAMS1_23 BIT_32(23)
280 #define _DWC3_GHWPARAMS1_GHWPARAMS1_26 BIT_32(26)
281 #define _DWC3_GHWPARAMS1_GHWPARAMS1_27 BIT_32(27)
282 #define _DWC3_GHWPARAMS1_GHWPARAMS1_28 BIT_32(28)
283 #define _DWC3_GHWPARAMS1_GHWPARAMS1_29 BIT_32(29)
284 #define _DWC3_GHWPARAMS1_GHWPARAMS1_30 BIT_32(30)
285 #define _DWC3_GHWPARAMS1_GHWPARAMS1_31 BIT_32(31)
298 #define _DWC3_GHWPARAMS3_GHWPARAMS3_10 BIT_32(10)
299 #define _DWC3_GHWPARAMS3_GHWPARAMS3_11 BIT_32(11)
306 #define _DWC3_GHWPARAMS3_GHWPARAMS3_31 BIT_32(31)
311 #define _DWC3_GHWPARAMS4_GHWPARAMS4_6 BIT_32(6)
316 #define _DWC3_GHWPARAMS4_GHWPARAMS4_11 BIT_32(11)
317 #define _DWC3_GHWPARAMS4_GHWPARAMS4_12 BIT_32(12)
322 #define _DWC3_GHWPARAMS4_GHWPARAMS4_21 BIT_32(21)
323 #define _DWC3_GHWPARAMS4_GHWPARAMS4_22 BIT_32(22)
324 #define _DWC3_GHWPARAMS4_GHWPARAMS4_23 BIT_32(23)
347 #define _DWC3_GHWPARAMS6_GHWPARAMS6_6 BIT_32(6)
348 #define _DWC3_GHWPARAMS6_GHWPARAMS6_7 BIT_32(7)
351 #define _DWC3_GHWPARAMS6_SRPSUPPORT BIT_32(10)
352 #define _DWC3_GHWPARAMS6_HNPSUPPORT BIT_32(11)
353 #define _DWC3_GHWPARAMS6_ADPSUPPORT BIT_32(12)
354 #define _DWC3_GHWPARAMS6_OTG_SS_SUPPORT BIT_32(13)
355 #define _DWC3_GHWPARAMS6_BCSUPPORT BIT_32(14)
356 #define _DWC3_GHWPARAMS6_BUSFLTRSSUPPORT BIT_32(15)
373 #define _DWC3_GDBGLTSSM_TXONESZEROS BIT_32(0)
374 #define _DWC3_GDBGLTSSM_RXTERMINATION BIT_32(1)
375 #define _DWC3_GDBGLTSSM_TXSWING BIT_32(2)
380 #define _DWC3_GDBGLTSSM_RXEQTRAIN BIT_32(8)
385 #define _DWC3_GDBGLTSSM_TXDETRXLOOPBACK BIT_32(14)
386 #define _DWC3_GDBGLTSSM_RXPOLARITY BIT_32(15)
387 #define _DWC3_GDBGLTSSM_TXELECLDLE BIT_32(16)
388 #define _DWC3_GDBGLTSSM_ELASTICBUFFERMODE BIT_32(17)
393 #define _DWC3_GDBGLTSSM_LTDBTIMEOUT BIT_32(26)
394 #define _DWC3_GDBGLTSSM_PRTDIRECTION BIT_32(27)
395 #define _DWC3_GDBGLTSSM_X3_DS_HOST_SHUTDOWN BIT_32(28)
396 #define _DWC3_GDBGLTSSM_X3_XS_SWAPPING BIT_32(29)
397 #define _DWC3_GDBGLTSSM_RXELECIDLE BIT_32(30)
490 #define _DWC3_GUCTL2_DISABLECFC BIT_32(11)
491 #define _DWC3_GUCTL2_ENABLEEPCACHEEVICT BIT_32(12)
492 #define _DWC3_GUCTL2_RST_ACTBITLATER BIT_32(14)
519 #define _DWC3_GFLADJ_GFLADJ_30MHZ_SDBND_SEL BIT_32(7)
522 #define _DWC3_GFLADJ_GFLADJ_REFCLK_LPM_SEL BIT_32(23)
525 #define _DWC3_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1 BIT_32(31)
530 #define _DWC3_GUSB2PHYCFG_PHYIF BIT_32(3)
531 #define _DWC3_GUSB2PHYCFG_ULPI_UTMI_SEL BIT_32(4)
532 #define _DWC3_GUSB2PHYCFG_FSINTF BIT_32(5)
533 #define _DWC3_GUSB2PHYCFG_SUSPENDUSB20 BIT_32(6)
534 #define _DWC3_GUSB2PHYCFG_PHYSEL BIT_32(7)
535 #define _DWC3_GUSB2PHYCFG_ENBLSLPM BIT_32(8)
536 #define _DWC3_GUSB2PHYCFG_XCVRDLY BIT_32(9)
539 #define _DWC3_GUSB2PHYCFG_ULPIAUTORES BIT_32(15)
540 #define _DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT_32(17)
541 #define _DWC3_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR BIT_32(18)
546 #define _DWC3_GUSB2PHYCFG_INV_SEL_HSIC BIT_32(26)
549 #define _DWC3_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK BIT_32(29)
550 #define _DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT_32(30)
551 #define _DWC3_GUSB2PHYCFG_PHYSOFTRST BIT_32(31)
560 #define _DWC3_GUSB2PHYACC_ULPI_REGWR BIT_32(22)
561 #define _DWC3_GUSB2PHYACC_ULPI_VSTSBSY BIT_32(23)
562 #define _DWC3_GUSB2PHYACC_ULPI_VSTSDONE BIT_32(24)
563 #define _DWC3_GUSB2PHYACC_ULPI_NEWREGREQ BIT_32(25)
564 #define _DWC3_GUSB2PHYACC_ULPI_DISUIPIDRVR BIT_32(26)
567 #define _DWC3_GUSB3PIPECTL_ELASTIC_BUFFER_MODE BIT_32(0)
572 #define _DWC3_GUSB3PIPECTL_TX_SWING BIT_32(6)
573 #define _DWC3_GUSB3PIPECTL_SSICEN BIT_32(7)
574 #define _DWC3_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL BIT_32(8)
575 #define _DWC3_GUSB3PIPECTL_LFPSFILTER BIT_32(9)
576 #define _DWC3_GUSB3PIPECTL_P3EXSIGP2 BIT_32(10)
577 #define _DWC3_GUSB3PIPECTL_P3P2TRANOK BIT_32(11)
578 #define _DWC3_GUSB3PIPECTL_LFPSP0ALGN BIT_32(12)
579 #define _DWC3_GUSB3PIPECTL_SKIPRXDET BIT_32(13)
580 #define _DWC3_GUSB3PIPECTL_ABORTRXDETINU2 BIT_32(14)
583 #define _DWC3_GUSB3PIPECTL_SUSPENDENABLE BIT_32(17)
584 #define _DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT_32(18)
587 #define _DWC3_GUSB3PIPECTL_DISRXDETU3RXDET BIT_32(22)
588 #define _DWC3_GUSB3PIPECTL_STARTRXDETU3RXDET BIT_32(23)
589 #define _DWC3_GUSB3PIPECTL_REQUEST_P1P2P3 BIT_32(24)
590 #define _DWC3_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV BIT_32(25)
591 #define _DWC3_GUSB3PIPECTL_PING_ENHANCEMENT_EN BIT_32(26)
592 #define _DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT_32(27)
593 #define _DWC3_GUSB3PIPECTL_DISRXDETP3 BIT_32(28)
594 #define _DWC3_GUSB3PIPECTL_U2P3OK BIT_32(29)
595 #define _DWC3_GUSB3PIPECTL_HSTPRTCMPL BIT_32(30)
596 #define _DWC3_GUSB3PIPECTL_PHYSOFTRST BIT_32(31)
691 #define _DWC3_GEVNTSIZ_EVNTINTRPTMASK BIT_32(31)
696 #define _DWC3_GEVNTCOUNT_EVNT_HANDLER_BUSY BIT_32(31)
723 #define _DWC3_DCFG_LPMCAP BIT_32(22)
724 #define _DWC3_DCFG_IGNSTRMPP BIT_32(23)
731 #define _DWC3_DCTL_ACCEPTU1ENA BIT_32(9)
732 #define _DWC3_DCTL_INITU1ENA BIT_32(10)
733 #define _DWC3_DCTL_ACCEPTU2ENA BIT_32(11)
734 #define _DWC3_DCTL_INITU2ENA BIT_32(12)
735 #define _DWC3_DCTL_CSS BIT_32(16)
736 #define _DWC3_DCTL_CRS BIT_32(17)
737 #define _DWC3_DCTL_L1HIBERNATIONEN BIT_32(18)
738 #define _DWC3_DCTL_KEEPCONNECT BIT_32(19)
743 #define _DWC3_DCTL_CSFTRST BIT_32(30)
744 #define _DWC3_DCTL_RUN_STOP BIT_32(31)
747 #define _DWC3_DEVTEN_DISSCONNEVTEN BIT_32(0)
748 #define _DWC3_DEVTEN_USBRSTEVTEN BIT_32(1)
749 #define _DWC3_DEVTEN_CONNECTDONEEVTEN BIT_32(2)
750 #define _DWC3_DEVTEN_ULSTCNGEN BIT_32(3)
751 #define _DWC3_DEVTEN_WKUPEVTEN BIT_32(4)
752 #define _DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT_32(5)
753 #define _DWC3_DEVTEN_U3L2L1SUSPEN BIT_32(6)
754 #define _DWC3_DEVTEN_SOFTEVTEN BIT_32(7)
755 #define _DWC3_DEVTEN_L1SUSPEN BIT_32(8)
756 #define _DWC3_DEVTEN_ERRTICERREVTEN BIT_32(9)
757 #define _DWC3_DEVTEN_CMDCMPLTEN BIT_32(10)
758 #define _DWC3_DEVTEN_EVNTOVERFLOWEN BIT_32(11)
759 #define _DWC3_DEVTEN_VENDEVTSTRCVDEN BIT_32(12)
760 #define _DWC3_DEVTEN_L1WKUPEVTEN BIT_32(14)
761 #define _DWC3_DEVTEN_ECCERREN BIT_32(16)
768 #define _DWC3_DSTS_RXFIFOEMPTY BIT_32(17)
771 #define _DWC3_DSTS_DEVCTRLHLT BIT_32(22)
772 #define _DWC3_DSTS_COREIDLE BIT_32(23)
773 #define _DWC3_DSTS_SSS BIT_32(24)
774 #define _DWC3_DSTS_RSS BIT_32(25)
775 #define _DWC3_DSTS_SRE BIT_32(28)
776 #define _DWC3_DSTS_DCNRD BIT_32(29)
781 #define _DWC3_DGCMD_CMDIOC BIT_32(8)
782 #define _DWC3_DGCMD_CMDACT BIT_32(10)
789 #define _DWC3_DEPCMD_CMDIOC BIT_32(8)
790 #define _DWC3_DEPCMD_CMDACT BIT_32(10)
791 #define _DWC3_DEPCMD_HIPRI_FORCERM BIT_32(11)
811 #define _DWC3_BCFG_CHIRP_EN BIT_32(0)
812 #define _DWC3_BCFG_IDDIG_SEL BIT_32(1)
817 #define _DWC3_BCEVT_MV_CHNGEVNT BIT_32(24)
820 #define _DWC3_BCEVTEN_MV_CHNGEVNTENA BIT_32(24)
855 #define _DWC3_HCSPARAMS2_SPR BIT_32(26)
866 #define _DWC3_HCCPARAMS1_AC64 BIT_32(0)
867 #define _DWC3_HCCPARAMS1_BNC BIT_32(1)
868 #define _DWC3_HCCPARAMS1_CSZ BIT_32(2)
869 #define _DWC3_HCCPARAMS1_PPC BIT_32(3)
870 #define _DWC3_HCCPARAMS1_PIND BIT_32(4)
871 #define _DWC3_HCCPARAMS1_LHRC BIT_32(5)
872 #define _DWC3_HCCPARAMS1_LTC BIT_32(6)
873 #define _DWC3_HCCPARAMS1_NSS BIT_32(7)
874 #define _DWC3_HCCPARAMS1_PAE BIT_32(8)
875 #define _DWC3_HCCPARAMS1_SPC BIT_32(9)
876 #define _DWC3_HCCPARAMS1_SEC BIT_32(10)
877 #define _DWC3_HCCPARAMS1_CFC BIT_32(11)
892 #define _DWC3_HCCPARAMS2_U3C BIT_32(0)
893 #define _DWC3_HCCPARAMS2_CMC BIT_32(1)
894 #define _DWC3_HCCPARAMS2_FSC BIT_32(2)
895 #define _DWC3_HCCPARAMS2_CTC BIT_32(3)
896 #define _DWC3_HCCPARAMS2_LEC BIT_32(4)
897 #define _DWC3_HCCPARAMS2_CIC BIT_32(5)
913 #define _DWC3_USBCMD_R_S BIT_32(0)
914 #define _DWC3_USBCMD_HCRST BIT_32(1)
915 #define _DWC3_USBCMD_INTE BIT_32(2)
916 #define _DWC3_USBCMD_HSEE BIT_32(3)
917 #define _DWC3_USBCMD_LHCRST BIT_32(7)
918 #define _DWC3_USBCMD_CSS BIT_32(8)
919 #define _DWC3_USBCMD_CRS BIT_32(9)
920 #define _DWC3_USBCMD_EWE BIT_32(10)
921 #define _DWC3_USBCMD_EU3S BIT_32(11)
922 #define _DWC3_USBCMD_CME BIT_32(13)
925 #define _DWC3_USBSTS_HCH BIT_32(0)
926 #define _DWC3_USBSTS_HSE BIT_32(2)
927 #define _DWC3_USBSTS_EINT BIT_32(3)
928 #define _DWC3_USBSTS_PCD BIT_32(4)
929 #define _DWC3_USBSTS_SSS BIT_32(8)
930 #define _DWC3_USBSTS_RSS BIT_32(9)
931 #define _DWC3_USBSTS_SRE BIT_32(10)
932 #define _DWC3_USBSTS_CNR BIT_32(11)
933 #define _DWC3_USBSTS_HCE BIT_32(12)
944 #define _DWC3_CRCR_LO_RCS BIT_32(0)
945 #define _DWC3_CRCR_LO_CS BIT_32(1)
946 #define _DWC3_CRCR_LO_CA BIT_32(2)
947 #define _DWC3_CRCR_LO_CRR BIT_32(3)
958 #define _DWC3_CONFIG_U3E BIT_32(8)
959 #define _DWC3_CONFIG_CIE BIT_32(9)
974 #define _DWC3_PORTSC_20_CCS BIT_32(0)
975 #define _DWC3_PORTSC_20_PED BIT_32(1)
976 #define _DWC3_PORTSC_20_OCA BIT_32(3)
977 #define _DWC3_PORTSC_20_PR BIT_32(4)
980 #define _DWC3_PORTSC_20_PP BIT_32(9)
985 #define _DWC3_PORTSC_20_LWS BIT_32(16)
986 #define _DWC3_PORTSC_20_CSC BIT_32(17)
987 #define _DWC3_PORTSC_20_PEC BIT_32(18)
988 #define _DWC3_PORTSC_20_OCC BIT_32(20)
989 #define _DWC3_PORTSC_20_PRC BIT_32(21)
990 #define _DWC3_PORTSC_20_PLC BIT_32(22)
991 #define _DWC3_PORTSC_20_CAS BIT_32(24)
992 #define _DWC3_PORTSC_20_WCE BIT_32(25)
993 #define _DWC3_PORTSC_20_WDE BIT_32(26)
994 #define _DWC3_PORTSC_20_WOE BIT_32(27)
995 #define _DWC3_PORTSC_20_DR BIT_32(30)
1000 #define _DWC3_PORTPMSC_20_RWE BIT_32(3)
1005 #define _DWC3_PORTPMSC_20_HLE BIT_32(16)
1018 #define _DWC3_PORTSC_30_CCS BIT_32(0)
1019 #define _DWC3_PORTSC_30_PED BIT_32(1)
1020 #define _DWC3_PORTSC_30_OCA BIT_32(3)
1021 #define _DWC3_PORTSC_30_PR BIT_32(4)
1024 #define _DWC3_PORTSC_30_PP BIT_32(9)
1029 #define _DWC3_PORTSC_30_LWS BIT_32(16)
1030 #define _DWC3_PORTSC_30_CSC BIT_32(17)
1031 #define _DWC3_PORTSC_30_PEC BIT_32(18)
1032 #define _DWC3_PORTSC_30_WRC BIT_32(19)
1033 #define _DWC3_PORTSC_30_OCC BIT_32(20)
1034 #define _DWC3_PORTSC_30_PRC BIT_32(21)
1035 #define _DWC3_PORTSC_30_PLC BIT_32(22)
1036 #define _DWC3_PORTSC_30_CEC BIT_32(23)
1037 #define _DWC3_PORTSC_30_CAS BIT_32(24)
1038 #define _DWC3_PORTSC_30_WCE BIT_32(25)
1039 #define _DWC3_PORTSC_30_WDE BIT_32(26)
1040 #define _DWC3_PORTSC_30_WOE BIT_32(27)
1041 #define _DWC3_PORTSC_30_DR BIT_32(30)
1042 #define _DWC3_PORTSC_30_WPR BIT_32(31)
1049 #define _DWC3_PORTPMSC_30_FLA BIT_32(16)
1076 #define _DWC3_IMAN_IP BIT_32(0)
1077 #define _DWC3_IMAN_IE BIT_32(1)
1096 #define _DWC3_ERDP_LO_EHB BIT_32(3)
1142 #define _DWC3_USBLEGSUP_HC_BIOS_OWNED BIT_32(16)
1143 #define _DWC3_USBLEGSUP_HC_OS_OWNED BIT_32(24)
1146 #define _DWC3_USBLEGCTLSTS_USB_SMI_ENABLE BIT_32(0)
1147 #define _DWC3_USBLEGCTLSTS_SMI_ON_HOST_E BIT_32(4)
1148 #define _DWC3_USBLEGCTLSTS_SMI_ON_OS_E BIT_32(13)
1149 #define _DWC3_USBLEGCTLSTS_SMI_ON_PCI_E BIT_32(14)
1150 #define _DWC3_USBLEGCTLSTS_SMI_ON_BAR_E BIT_32(15)
1151 #define _DWC3_USBLEGCTLSTS_SMI_ON_EVENT BIT_32(16)
1152 #define _DWC3_USBLEGCTLSTS_SMI_ON_HOST BIT_32(20)
1153 #define _DWC3_USBLEGCTLSTS_SMI_ON_OS BIT_32(29)
1154 #define _DWC3_USBLEGCTLSTS_SMI_ON_PCI BIT_32(30)
1155 #define _DWC3_USBLEGCTLSTS_SMI_ON_BAR BIT_32(31)
1180 #define _DWC3_SUPTPRT2_DW2_HSO BIT_32(17)
1181 #define _DWC3_SUPTPRT2_DW2_IHI BIT_32(18)
1182 #define _DWC3_SUPTPRT2_DW2_HLC BIT_32(19)
1183 #define _DWC3_SUPTPRT2_DW2_BLC BIT_32(20)