1*7b4b208eSNicolas Le Bayon /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*7b4b208eSNicolas Le Bayon /* 3*7b4b208eSNicolas Le Bayon * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4*7b4b208eSNicolas Le Bayon * 5*7b4b208eSNicolas Le Bayon */ 6*7b4b208eSNicolas Le Bayon 7*7b4b208eSNicolas Le Bayon #ifndef _DT_BINDINGS_RIF_H 8*7b4b208eSNicolas Le Bayon #define _DT_BINDINGS_RIF_H 9*7b4b208eSNicolas Le Bayon 10*7b4b208eSNicolas Le Bayon /* RIFSC CIDs */ 11*7b4b208eSNicolas Le Bayon #define RIF_CID0 0x0 12*7b4b208eSNicolas Le Bayon #define RIF_CID1 0x1 13*7b4b208eSNicolas Le Bayon #define RIF_CID2 0x2 14*7b4b208eSNicolas Le Bayon #define RIF_CID3 0x3 15*7b4b208eSNicolas Le Bayon #define RIF_CID4 0x4 16*7b4b208eSNicolas Le Bayon #define RIF_CID5 0x5 17*7b4b208eSNicolas Le Bayon #define RIF_CID6 0x6 18*7b4b208eSNicolas Le Bayon #define RIF_CID7 0x7 19*7b4b208eSNicolas Le Bayon #define RIF_CID_MAX 0x8 20*7b4b208eSNicolas Le Bayon 21*7b4b208eSNicolas Le Bayon /* RIFSC semaphore list */ 22*7b4b208eSNicolas Le Bayon #define EMPTY_SEMWL 0x0 23*7b4b208eSNicolas Le Bayon #define RIF_CID0_BF BIT_32(RIF_CID0) 24*7b4b208eSNicolas Le Bayon #define RIF_CID1_BF BIT_32(RIF_CID1) 25*7b4b208eSNicolas Le Bayon #define RIF_CID2_BF BIT_32(RIF_CID2) 26*7b4b208eSNicolas Le Bayon #define RIF_CID3_BF BIT_32(RIF_CID3) 27*7b4b208eSNicolas Le Bayon #define RIF_CID4_BF BIT_32(RIF_CID4) 28*7b4b208eSNicolas Le Bayon #define RIF_CID5_BF BIT_32(RIF_CID5) 29*7b4b208eSNicolas Le Bayon #define RIF_CID6_BF BIT_32(RIF_CID6) 30*7b4b208eSNicolas Le Bayon #define RIF_CID7_BF BIT_32(RIF_CID7) 31*7b4b208eSNicolas Le Bayon 32*7b4b208eSNicolas Le Bayon /* RIFSC secure levels */ 33*7b4b208eSNicolas Le Bayon #define RIF_NSEC 0x0 34*7b4b208eSNicolas Le Bayon #define RIF_SEC 0x1 35*7b4b208eSNicolas Le Bayon 36*7b4b208eSNicolas Le Bayon /* RIFSC privilege levels */ 37*7b4b208eSNicolas Le Bayon #define RIF_NPRIV 0x0 38*7b4b208eSNicolas Le Bayon #define RIF_PRIV 0x1 39*7b4b208eSNicolas Le Bayon 40*7b4b208eSNicolas Le Bayon /* RIFSC semaphore modes */ 41*7b4b208eSNicolas Le Bayon #define RIF_SEM_DIS 0x0 42*7b4b208eSNicolas Le Bayon #define RIF_SEM_EN 0x1 43*7b4b208eSNicolas Le Bayon 44*7b4b208eSNicolas Le Bayon /* RIFSC CID filtering modes */ 45*7b4b208eSNicolas Le Bayon #define RIF_CFDIS 0x0 46*7b4b208eSNicolas Le Bayon #define RIF_CFEN 0x1 47*7b4b208eSNicolas Le Bayon 48*7b4b208eSNicolas Le Bayon /* RIFSC lock states */ 49*7b4b208eSNicolas Le Bayon #define RIF_UNLOCK 0x0 50*7b4b208eSNicolas Le Bayon #define RIF_LOCK 0x1 51*7b4b208eSNicolas Le Bayon 52*7b4b208eSNicolas Le Bayon /* Used when a field in a macro has no impact */ 53*7b4b208eSNicolas Le Bayon #define RIF_UNUSED 0x0 54*7b4b208eSNicolas Le Bayon 55*7b4b208eSNicolas Le Bayon #define RIFPROT(rifid, sem_list, sec, priv, scid, sem_en, cfen) \ 56*7b4b208eSNicolas Le Bayon (((rifid) << 24) | ((sem_list) << 16) | ((priv) << 9) | ((sec) << 8) | ((scid) << 4) | \ 57*7b4b208eSNicolas Le Bayon ((sem_en) << 1) | (cfen)) 58*7b4b208eSNicolas Le Bayon 59*7b4b208eSNicolas Le Bayon /* Masters IDs */ 60*7b4b208eSNicolas Le Bayon #define RIMU_ID(idx) (idx) 61*7b4b208eSNicolas Le Bayon 62*7b4b208eSNicolas Le Bayon /* Master configuration modes */ 63*7b4b208eSNicolas Le Bayon #define RIF_CIDSEL_P 0x0 /* Config from RISUP */ 64*7b4b208eSNicolas Le Bayon #define RIF_CIDSEL_M 0x1 /* Config from RIMU */ 65*7b4b208eSNicolas Le Bayon 66*7b4b208eSNicolas Le Bayon #define RIMUPROT(rimuid, scid, sec, priv, mode) \ 67*7b4b208eSNicolas Le Bayon (((rimuid) << 16) | ((priv) << 9) | ((sec) << 8) | ((scid) << 4) | ((mode) << 2)) 68*7b4b208eSNicolas Le Bayon 69*7b4b208eSNicolas Le Bayon /* RISAF region IDs */ 70*7b4b208eSNicolas Le Bayon #define RISAF_REG_ID(idx) (idx) 71*7b4b208eSNicolas Le Bayon 72*7b4b208eSNicolas Le Bayon /* RISAF base region enable modes */ 73*7b4b208eSNicolas Le Bayon #define RIF_BREN_DIS 0x0 74*7b4b208eSNicolas Le Bayon #define RIF_BREN_EN 0x1 75*7b4b208eSNicolas Le Bayon 76*7b4b208eSNicolas Le Bayon /* RISAF encryption modes */ 77*7b4b208eSNicolas Le Bayon #define RIF_ENC_DIS 0x0 78*7b4b208eSNicolas Le Bayon #define RIF_ENC_EN 0x1 79*7b4b208eSNicolas Le Bayon 80*7b4b208eSNicolas Le Bayon #define RISAFPROT(risaf_region, cid_read_list, cid_write_list, cid_priv_list, sec, enc, enabled) \ 81*7b4b208eSNicolas Le Bayon (((cid_write_list) << 24) | ((cid_read_list) << 16) | ((cid_priv_list) << 8) | \ 82*7b4b208eSNicolas Le Bayon ((enc) << 7) | ((sec) << 6) | ((enabled) << 5) | (risaf_region)) 83*7b4b208eSNicolas Le Bayon 84*7b4b208eSNicolas Le Bayon /* RISAB page IDs */ 85*7b4b208eSNicolas Le Bayon #define RISAB_PAGE_ID(idx) (idx) 86*7b4b208eSNicolas Le Bayon 87*7b4b208eSNicolas Le Bayon /* RISAB control modes */ 88*7b4b208eSNicolas Le Bayon #define RIF_DDCID_DIS 0x0 89*7b4b208eSNicolas Le Bayon #define RIF_DDCID_EN 0x1 90*7b4b208eSNicolas Le Bayon 91*7b4b208eSNicolas Le Bayon #define RISABPROT(risab_page, delegate_en, delegate_cid, sec, default_priv, cid_read_list, \ 92*7b4b208eSNicolas Le Bayon cid_write_list, cid_priv_list, enabled) \ 93*7b4b208eSNicolas Le Bayon (((risab_page) << 24) | ((default_priv) << 9) | ((sec) << 8) | ((delegate_cid) << 4) | \ 94*7b4b208eSNicolas Le Bayon ((delegate_en) << 2) | (enabled)) \ 95*7b4b208eSNicolas Le Bayon ((cid_write_list) << 16 | (cid_read_list) << 8 | (cid_priv_list)) 96*7b4b208eSNicolas Le Bayon 97*7b4b208eSNicolas Le Bayon #endif /* _DT_BINDINGS_RIF_H */ 98