| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | platform_config.h | 24 #define GICC_BASE (GIC_BASE + 0x2000) macro
51 #define GICC_BASE (MMIO_BASE + 0x07F00000) macro
75 #define GICC_BASE (GIC_BASE + 0x2000) macro
93 #define GICC_BASE 0 macro
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| H A D | main.c | 34 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-marvell/ |
| H A D | main.c | 70 #ifdef GICC_BASE
71 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, CORE_MMU_PGDIR_SIZE);
79 #ifdef GICC_BASE in boot_primary_init_intc()
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| H A D | platform_config.h | 73 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
104 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
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| /optee_os/core/arch/arm/plat-corstone1000/ |
| H A D | main.c | 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
33 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 40 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
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| /optee_os/core/arch/arm/plat-automotive_rd/ |
| H A D | main.c | 24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
34 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 59 #define GICC_BASE UL(0x2C000000) macro
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| /optee_os/core/arch/arm/plat-rcar/ |
| H A D | platform_config.h | 42 #define GICC_BASE 0xF1020000 macro
51 #define GICC_BASE 0xF1060000 macro
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| H A D | main.c | 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
92 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-ti/ |
| H A D | platform_config.h | 44 #define GICC_BASE (SCU_BASE + GICC_OFFSET) macro
81 #define GICC_BASE (SCU_BASE + GICC_OFFSET) macro
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| H A D | main.c | 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
39 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-nuvoton/ |
| H A D | main.c | 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
60 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 23 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
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| /optee_os/core/arch/arm/plat-k3/ |
| H A D | main.c | 23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
48 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 72 #define GICC_BASE (SCU_BASE + GICC_OFFSET) macro
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| /optee_os/core/arch/arm/plat-rzn1/ |
| H A D | platform_config.h | 21 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
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| H A D | main.c | 45 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-totalcompute/ |
| H A D | platform_config.h | 43 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
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| /optee_os/core/arch/arm/plat-rzg/ |
| H A D | platform_config.h | 16 #define GICC_BASE 0xF1020000 macro
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| H A D | main.c | 16 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
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| /optee_os/core/arch/arm/plat-telechips/tcc805x/ |
| H A D | platform_config.h | 21 #define GICC_BASE U(0x17302000) macro
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| /optee_os/core/arch/arm/plat-telechips/ |
| H A D | main.c | 31 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-vexpress/ |
| H A D | platform_config.h | 160 #define GICC_BASE (GIC_BASE + GICC_OFFSET) macro
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| H A D | main.c | 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
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