1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2022, Arm Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 64 13 14 #define GIC_BASE 0x1c000000 15 16 #define UART0_BASE 0x1a510000 17 #define UART1_BASE 0x1a520000 18 #define CONSOLE_UART_BASE UART1_BASE 19 20 #define DRAM0_BASE 0x80000000 21 #define DRAM0_SIZE CFG_DDR_SIZE 22 23 #define GICD_OFFSET 0x10000 24 #define GICC_OFFSET 0x2F000 25 26 #define GICD_BASE (GIC_BASE + GICD_OFFSET) 27 #define GICC_BASE (GIC_BASE + GICC_OFFSET) 28 29 #define UART_BAUDRATE 115200 30 #define CONSOLE_BAUDRATE UART_BAUDRATE 31 32 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ 33 34 #define CONSOLE_UART_CLK_IN_HZ UL(50000000) /* 50MHz*/ 35 36 #endif /*PLATFORM_CONFIG_H*/ 37