xref: /optee_os/core/arch/arm/plat-rzg/main.c (revision 55ab8f06a831946a49717446cd2e4495a2b5d659)
14055cfc4SLad Prabhakar // SPDX-License-Identifier: BSD-2-Clause
24055cfc4SLad Prabhakar /*
34055cfc4SLad Prabhakar  * Copyright (c) 2016, GlobalLogic
44055cfc4SLad Prabhakar  * Copyright (c) 2019-2020, Renesas Electronics Corporation
54055cfc4SLad Prabhakar  */
64055cfc4SLad Prabhakar 
74055cfc4SLad Prabhakar #include <console.h>
84055cfc4SLad Prabhakar #include <drivers/gic.h>
94055cfc4SLad Prabhakar #include <drivers/scif.h>
104055cfc4SLad Prabhakar #include <kernel/panic.h>
114055cfc4SLad Prabhakar #include <mm/core_memprot.h>
124055cfc4SLad Prabhakar #include <platform_config.h>
134055cfc4SLad Prabhakar 
144055cfc4SLad Prabhakar register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
154055cfc4SLad Prabhakar register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
164055cfc4SLad Prabhakar register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
174055cfc4SLad Prabhakar 
184055cfc4SLad Prabhakar register_dynamic_shm(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);
194055cfc4SLad Prabhakar #ifdef NSEC_DDR_1_BASE
204055cfc4SLad Prabhakar register_dynamic_shm(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE);
214055cfc4SLad Prabhakar #endif
224055cfc4SLad Prabhakar #ifdef NSEC_DDR_2_BASE
234055cfc4SLad Prabhakar register_dynamic_shm(NSEC_DDR_2_BASE, NSEC_DDR_2_SIZE);
244055cfc4SLad Prabhakar #endif
254055cfc4SLad Prabhakar #ifdef NSEC_DDR_3_BASE
264055cfc4SLad Prabhakar register_dynamic_shm(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE);
274055cfc4SLad Prabhakar #endif
284055cfc4SLad Prabhakar 
294055cfc4SLad Prabhakar static struct scif_uart_data console_data __nex_bss;
304055cfc4SLad Prabhakar 
plat_console_init(void)31*55ab8f06SAlvin Chang void plat_console_init(void)
324055cfc4SLad Prabhakar {
334055cfc4SLad Prabhakar 	scif_uart_init(&console_data, CONSOLE_UART_BASE);
344055cfc4SLad Prabhakar 	register_serial_console(&console_data.chip);
354055cfc4SLad Prabhakar }
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