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Searched refs:CCR (Results 1 – 25 of 58) sorted by relevance

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/OK3568_Linux_fs/kernel/arch/arm/plat-omap/
H A Ddma.c160 ccr = p->dma_read(CCR, lch); in omap_set_dma_priority()
165 p->dma_write(ccr, CCR, lch); in omap_set_dma_priority()
184 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
188 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
200 val = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
225 p->dma_write(val, CCR, lch); in omap_set_dma_transfer_params()
262 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
265 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
343 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
346 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
[all …]
/OK3568_Linux_fs/kernel/drivers/dma/
H A Dtxx9dmac.h77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
H A Dtxx9dmac.c295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
/OK3568_Linux_fs/u-boot/arch/sh/cpu/sh4/
H A Dcache.c43 ccr = inl(CCR); in cache_control()
49 outl(CCR_CACHE_STOP, CCR); in cache_control()
51 outl(CCR_CACHE_INIT, CCR); in cache_control()
/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A Dpm-imx6.c29 #define CCR 0x0 macro
253 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
256 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
259 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
262 writel(val, ccm_base + CCR); in imx6_enable_rbc()
286 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
289 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-atmel-tcb.c104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
324 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
332 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
348 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.ne20003 that the CCR is correctly initialized.
26 - Address of the CCR (card configuration register). It could be found
32 - The value to be written in the CCR. It selects among different I/O
/OK3568_Linux_fs/kernel/arch/arm/mach-omap1/
H A Ddma.c57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-atmel-tcb.c189 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
193 ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
277 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_enable()
493 base + ATMEL_TC_REG(i, CCR)); in atmel_tcb_pwm_resume()
/OK3568_Linux_fs/u-boot/arch/sh/include/asm/
H A Dcpu_sh7763.h12 #define CCR 0xFF00001C macro
H A Dcpu_sh7269.h6 #define CCR CCR1 macro
H A Dcpu_sh7203.h6 #define CCR CCR1 macro
H A Dcpu_sh7264.h6 #define CCR CCR1 macro
H A Dcpu_sh7706.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7710.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7734.h12 #define CCR 0xFF00001C macro
H A Dcpu_sh7750.h29 #define CCR 0xFF00001C macro
H A Dcpu_sh7785.h21 #define CCR 0xFF00001C macro
H A Dcpu_sh7723.h30 #define CCR 0xFF00001C macro
H A Dcpu_sh7724.h30 #define CCR 0xFF00001C macro
/OK3568_Linux_fs/buildroot/board/csky/gx6605s/
H A Dgdbinit4 # setup CCR (Cache Config Reg)
/OK3568_Linux_fs/kernel/drivers/dma/ti/
H A Domap-dma.c457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
926 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1538 if (omap_dma_chan_read(c, CCR) & CCR_ENABLE) in omap_dma_busy()
/OK3568_Linux_fs/kernel/drivers/counter/
H A Dmicrochip-tcb-capture.c141 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_set()
148 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_set()
/OK3568_Linux_fs/u-boot/board/renesas/r2dplus/
H A Dlowlevel_init.S73 CCR_A: .long CCR /* Cache Control Register */
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Ddma.c53 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },

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