1*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7785_H_ 2*4882a593Smuzhiyun #define _ASM_CPU_SH7785_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 6*4882a593Smuzhiyun * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> 7*4882a593Smuzhiyun * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 1 13*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000090b 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Exceptions */ 16*4882a593Smuzhiyun #define TRA 0xFF000020 17*4882a593Smuzhiyun #define EXPEVT 0xFF000024 18*4882a593Smuzhiyun #define INTEVT 0xFF000028 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Cache Controller */ 21*4882a593Smuzhiyun #define CCR 0xFF00001C 22*4882a593Smuzhiyun #define QACR0 0xFF000038 23*4882a593Smuzhiyun #define QACR1 0xFF00003C 24*4882a593Smuzhiyun #define RAMCR 0xFF000074 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Watchdog Timer and Reset */ 27*4882a593Smuzhiyun #define WTCNT WDTCNT 28*4882a593Smuzhiyun #define WDTST 0xFFCC0000 29*4882a593Smuzhiyun #define WDTCSR 0xFFCC0004 30*4882a593Smuzhiyun #define WDTBST 0xFFCC0008 31*4882a593Smuzhiyun #define WDTCNT 0xFFCC0010 32*4882a593Smuzhiyun #define WDTBCNT 0xFFCC0018 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Timer Unit */ 35*4882a593Smuzhiyun #define TMU_BASE 0xFFD80000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Serial Communication Interface with FIFO */ 38*4882a593Smuzhiyun #define SCIF1_BASE 0xffeb0000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* LBSC */ 41*4882a593Smuzhiyun #define MMSELR 0xfc400020 42*4882a593Smuzhiyun #define LBSC_BASE 0xff800000 43*4882a593Smuzhiyun #define BCR (LBSC_BASE + 0x1000) 44*4882a593Smuzhiyun #define CS0BCR (LBSC_BASE + 0x2000) 45*4882a593Smuzhiyun #define CS1BCR (LBSC_BASE + 0x2010) 46*4882a593Smuzhiyun #define CS2BCR (LBSC_BASE + 0x2020) 47*4882a593Smuzhiyun #define CS3BCR (LBSC_BASE + 0x2030) 48*4882a593Smuzhiyun #define CS4BCR (LBSC_BASE + 0x2040) 49*4882a593Smuzhiyun #define CS5BCR (LBSC_BASE + 0x2050) 50*4882a593Smuzhiyun #define CS6BCR (LBSC_BASE + 0x2060) 51*4882a593Smuzhiyun #define CS0WCR (LBSC_BASE + 0x2008) 52*4882a593Smuzhiyun #define CS1WCR (LBSC_BASE + 0x2018) 53*4882a593Smuzhiyun #define CS2WCR (LBSC_BASE + 0x2028) 54*4882a593Smuzhiyun #define CS3WCR (LBSC_BASE + 0x2038) 55*4882a593Smuzhiyun #define CS4WCR (LBSC_BASE + 0x2048) 56*4882a593Smuzhiyun #define CS5WCR (LBSC_BASE + 0x2058) 57*4882a593Smuzhiyun #define CS6WCR (LBSC_BASE + 0x2068) 58*4882a593Smuzhiyun #define CS5PCR (LBSC_BASE + 0x2070) 59*4882a593Smuzhiyun #define CS6PCR (LBSC_BASE + 0x2080) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* PCI Controller */ 62*4882a593Smuzhiyun #define SH7780_PCIECR 0xFE000008 63*4882a593Smuzhiyun #define SH7780_PCIVID 0xFE040000 64*4882a593Smuzhiyun #define SH7780_PCIDID 0xFE040002 65*4882a593Smuzhiyun #define SH7780_PCICMD 0xFE040004 66*4882a593Smuzhiyun #define SH7780_PCISTATUS 0xFE040006 67*4882a593Smuzhiyun #define SH7780_PCIRID 0xFE040008 68*4882a593Smuzhiyun #define SH7780_PCIPIF 0xFE040009 69*4882a593Smuzhiyun #define SH7780_PCISUB 0xFE04000A 70*4882a593Smuzhiyun #define SH7780_PCIBCC 0xFE04000B 71*4882a593Smuzhiyun #define SH7780_PCICLS 0xFE04000C 72*4882a593Smuzhiyun #define SH7780_PCILTM 0xFE04000D 73*4882a593Smuzhiyun #define SH7780_PCIHDR 0xFE04000E 74*4882a593Smuzhiyun #define SH7780_PCIBIST 0xFE04000F 75*4882a593Smuzhiyun #define SH7780_PCIIBAR 0xFE040010 76*4882a593Smuzhiyun #define SH7780_PCIMBAR0 0xFE040014 77*4882a593Smuzhiyun #define SH7780_PCIMBAR1 0xFE040018 78*4882a593Smuzhiyun #define SH7780_PCISVID 0xFE04002C 79*4882a593Smuzhiyun #define SH7780_PCISID 0xFE04002E 80*4882a593Smuzhiyun #define SH7780_PCICP 0xFE040034 81*4882a593Smuzhiyun #define SH7780_PCIINTLINE 0xFE04003C 82*4882a593Smuzhiyun #define SH7780_PCIINTPIN 0xFE04003D 83*4882a593Smuzhiyun #define SH7780_PCIMINGNT 0xFE04003E 84*4882a593Smuzhiyun #define SH7780_PCIMAXLAT 0xFE04003F 85*4882a593Smuzhiyun #define SH7780_PCICID 0xFE040040 86*4882a593Smuzhiyun #define SH7780_PCINIP 0xFE040041 87*4882a593Smuzhiyun #define SH7780_PCIPMC 0xFE040042 88*4882a593Smuzhiyun #define SH7780_PCIPMCSR 0xFE040044 89*4882a593Smuzhiyun #define SH7780_PCIPMCSRBSE 0xFE040046 90*4882a593Smuzhiyun #define SH7780_PCI_CDD 0xFE040047 91*4882a593Smuzhiyun #define SH7780_PCICR 0xFE040100 92*4882a593Smuzhiyun #define SH7780_PCILSR0 0xFE040104 93*4882a593Smuzhiyun #define SH7780_PCILSR1 0xFE040108 94*4882a593Smuzhiyun #define SH7780_PCILAR0 0xFE04010C 95*4882a593Smuzhiyun #define SH7780_PCILAR1 0xFE040110 96*4882a593Smuzhiyun #define SH7780_PCIIR 0xFE040114 97*4882a593Smuzhiyun #define SH7780_PCIIMR 0xFE040118 98*4882a593Smuzhiyun #define SH7780_PCIAIR 0xFE04011C 99*4882a593Smuzhiyun #define SH7780_PCICIR 0xFE040120 100*4882a593Smuzhiyun #define SH7780_PCIAINT 0xFE040130 101*4882a593Smuzhiyun #define SH7780_PCIAINTM 0xFE040134 102*4882a593Smuzhiyun #define SH7780_PCIBMIR 0xFE040138 103*4882a593Smuzhiyun #define SH7780_PCIPAR 0xFE0401C0 104*4882a593Smuzhiyun #define SH7780_PCIPINT 0xFE0401CC 105*4882a593Smuzhiyun #define SH7780_PCIPINTM 0xFE0401D0 106*4882a593Smuzhiyun #define SH7780_PCIMBR0 0xFE0401E0 107*4882a593Smuzhiyun #define SH7780_PCIMBMR0 0xFE0401E4 108*4882a593Smuzhiyun #define SH7780_PCIMBR1 0xFE0401E8 109*4882a593Smuzhiyun #define SH7780_PCIMBMR1 0xFE0401EC 110*4882a593Smuzhiyun #define SH7780_PCIMBR2 0xFE0401F0 111*4882a593Smuzhiyun #define SH7780_PCIMBMR2 0xFE0401F4 112*4882a593Smuzhiyun #define SH7780_PCIIOBR 0xFE0401F8 113*4882a593Smuzhiyun #define SH7780_PCIIOBMR 0xFE0401FC 114*4882a593Smuzhiyun #define SH7780_PCICSCR0 0xFE040210 115*4882a593Smuzhiyun #define SH7780_PCICSCR1 0xFE040214 116*4882a593Smuzhiyun #define SH7780_PCICSAR0 0xFE040218 117*4882a593Smuzhiyun #define SH7780_PCICSAR1 0xFE04021C 118*4882a593Smuzhiyun #define SH7780_PCIPDR 0xFE040220 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7780_H_ */ 121