1*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7269_H_ 2*4882a593Smuzhiyun #define _ASM_CPU_SH7269_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Cache */ 5*4882a593Smuzhiyun #define CCR1 0xFFFC1000 6*4882a593Smuzhiyun #define CCR CCR1 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* SCIF */ 9*4882a593Smuzhiyun #define SCSMR_0 0xE8007000 10*4882a593Smuzhiyun #define SCIF0_BASE SCSMR_0 11*4882a593Smuzhiyun #define SCSMR_1 0xE8007800 12*4882a593Smuzhiyun #define SCIF1_BASE SCSMR_1 13*4882a593Smuzhiyun #define SCSMR_2 0xE8008000 14*4882a593Smuzhiyun #define SCIF2_BASE SCSMR_2 15*4882a593Smuzhiyun #define SCSMR_3 0xE8008800 16*4882a593Smuzhiyun #define SCIF3_BASE SCSMR_3 17*4882a593Smuzhiyun #define SCSMR_7 0xE800A800 18*4882a593Smuzhiyun #define SCIF7_BASE SCSMR_7 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Timer(CMT) */ 21*4882a593Smuzhiyun #define CMSTR 0xFFFEC000 22*4882a593Smuzhiyun #define CMCSR_0 0xFFFEC002 23*4882a593Smuzhiyun #define CMCNT_0 0xFFFEC004 24*4882a593Smuzhiyun #define CMCOR_0 0xFFFEC006 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7269_H_ */ 27