1*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7264_H_ 2*4882a593Smuzhiyun #define _ASM_CPU_SH7264_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Cache */ 5*4882a593Smuzhiyun #define CCR1 0xFFFC1000 6*4882a593Smuzhiyun #define CCR CCR1 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* PFC */ 9*4882a593Smuzhiyun #define PACR 0xA4050100 10*4882a593Smuzhiyun #define PBCR 0xA4050102 11*4882a593Smuzhiyun #define PCCR 0xA4050104 12*4882a593Smuzhiyun #define PETCR 0xA4050106 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Port Data Registers */ 15*4882a593Smuzhiyun #define PADR 0xA4050120 16*4882a593Smuzhiyun #define PBDR 0xA4050122 17*4882a593Smuzhiyun #define PCDR 0xA4050124 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* BSC */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* SDRAM controller */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* SCIF */ 24*4882a593Smuzhiyun #define SCSMR_3 0xFFFE9800 25*4882a593Smuzhiyun #define SCIF3_BASE SCSMR_3 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Timer(CMT) */ 28*4882a593Smuzhiyun #define CMSTR 0xFFFEC000 29*4882a593Smuzhiyun #define CMCSR_0 0xFFFEC002 30*4882a593Smuzhiyun #define CMCNT_0 0xFFFEC004 31*4882a593Smuzhiyun #define CMCOR_0 0xFFFEC006 32*4882a593Smuzhiyun #define CMCSR_1 0xFFFEC008 33*4882a593Smuzhiyun #define CMCNT_1 0xFFFEC00A 34*4882a593Smuzhiyun #define CMCOR_1 0xFFFEC00C 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* On chip oscillator circuits */ 37*4882a593Smuzhiyun #define FRQCR 0xA415FF80 38*4882a593Smuzhiyun #define WTCNT 0xA415FF84 39*4882a593Smuzhiyun #define WTCSR 0xA415FF86 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7264_H_ */ 42